Lines Matching +full:qcom +full:- +full:sm8450 +full:- +full:tlmm +full:- +full:state
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,sm8450-lpass-lpi-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SM8450 SoC LPASS LPI TLMM
10 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
14 (LPASS) Low Power Island (LPI) of Qualcomm SM8450 SoC.
18 const: qcom,sm8450-lpass-lpi-pinctrl
22 - description: LPASS LPI TLMM Control and Status registers
23 - description: LPASS LPI MCC registers
27 - description: LPASS Core voting clock
28 - description: LPASS Audio voting clock
30 clock-names:
32 - const: core
33 - const: audio
35 gpio-controller: true
37 "#gpio-cells":
39 include/dt-bindings/gpio/gpio.h
42 gpio-ranges:
46 "-state$":
48 - $ref: "#/$defs/qcom-sm8450-lpass-state"
49 - patternProperties:
50 "-pins$":
51 $ref: "#/$defs/qcom-sm8450-lpass-state"
55 qcom-sm8450-lpass-state:
60 $ref: /schemas/pinctrl/pincfg-node.yaml
68 pattern: "^gpio([0-9]|1[0-9]|2[0-2])$"
84 drive-strength:
90 slew-rate:
99 bias-bus-hold: true
100 bias-pull-down: true
101 bias-pull-up: true
102 bias-disable: true
103 input-enable: true
104 output-high: true
105 output-low: true
108 - pins
109 - function
114 - $ref: pinctrl.yaml#
117 - compatible
118 - reg
119 - clocks
120 - clock-names
121 - gpio-controller
122 - "#gpio-cells"
123 - gpio-ranges
128 - |
129 #include <dt-bindings/sound/qcom,q6afe.h>
131 compatible = "qcom,sm8450-lpass-lpi-pinctrl";
136 clock-names = "core", "audio";
137 gpio-controller;
138 #gpio-cells = <2>;
139 gpio-ranges = <&lpi_tlmm 0 0 23>;
141 wsa-swr-active-state {
142 clk-pins {
145 drive-strength = <2>;
146 slew-rate = <1>;
147 bias-disable;
150 data-pins {
153 drive-strength = <2>;
154 slew-rate = <1>;
158 tx-swr-sleep-clk-state {
161 drive-strength = <2>;
162 bias-pull-down;