bindings/pinctrl/qcom%2Csm6350-tlmm.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,sm6350-tlmm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Technologies, Inc. SM6350 TLMM block
10   - Konrad Dybcio <konrad.dybcio@somainline.org>
13   Top Level Mode Multiplexer pin controller in Qualcomm SM6350 SoC.
16   - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
20     const: qcom,sm6350-tlmm
29   interrupt-controller: true
30   "#interrupt-cells": true
31   gpio-controller: true
33   gpio-reserved-ranges:
37   gpio-line-names:
40   "#gpio-cells": true
41   gpio-ranges: true
42   wakeup-parent: true
45   - compatible
46   - reg
51   "-state$":
53       - $ref: "#/$defs/qcom-sm6350-tlmm-state"
54       - patternProperties:
55           "-pins$":
56             $ref: "#/$defs/qcom-sm6350-tlmm-state"
60   qcom-sm6350-tlmm-state:
65     $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
75             - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9]|15[0-5])$"
76             - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data ]
113       - pins
116   - |
117     #include <dt-bindings/interrupt-controller/arm-gic.h>
119         compatible = "qcom,sm6350-tlmm";
131         gpio-controller;
132         #gpio-cells = <2>;
133         interrupt-controller;
134         #interrupt-cells = <2>;
135         gpio-ranges = <&tlmm 0 0 157>;
137         gpio-wo-subnode-state {
142         uart-w-subnodes-state {
143             rx-pins {
146                 bias-disable;
149             tx-pins {
152                 bias-disable;