bindings/pinctrl/qcom%2Csdx75-tlmm.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,sdx75-tlmm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Rohit Agarwal <quic_rohiagar@quicinc.com>
16   - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
20     const: qcom,sdx75-tlmm
26   interrupt-controller: true
27   "#interrupt-cells": true
28   gpio-controller: true
30   gpio-reserved-ranges:
34   gpio-line-names:
37   "#gpio-cells": true
38   gpio-ranges: true
39   wakeup-parent: true
42   "-state$":
44       - $ref: "#/$defs/qcom-sdx75-tlmm-state"
45       - patternProperties:
46           "-pins$":
47             $ref: "#/$defs/qcom-sdx75-tlmm-state"
51   qcom-sdx75-tlmm-state:
54       Pinctrl node's client devices use subnodes for desired pin configuration.
55       Client device subnodes use below standard properties.
56     $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
66             - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-2][0-9]|13[0-2])$"
67             - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc1_rclk, sdc2_clk, sdc2_cmd, sdc2_data ]
97       - pins
100   - compatible
101   - reg
106   - |
107     #include <dt-bindings/interrupt-controller/arm-gic.h>
109         compatible = "qcom,sdx75-tlmm";
111         gpio-controller;
112         #gpio-cells = <2>;
113         gpio-ranges = <&tlmm 0 0 133>;
114         interrupt-controller;
115         #interrupt-cells = <2>;
118         gpio-wo-state {
123         uart-w-state {
124             rx-pins {
127                 bias-disable;
130             tx-pins {
133                 bias-disable;