bindings/pinctrl/qcom%2Csdx55-pinctrl.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,sdx55-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Technologies, Inc. SDX55 TLMM block
10   - Vinod Koul <vkoul@kernel.org>
17     const: qcom,sdx55-pinctrl
20     description: Specifies the base address and size of the TLMM register space
26   interrupt-controller: true
27   "#interrupt-cells": true
28   gpio-controller: true
29   "#gpio-cells": true
30   gpio-ranges: true
32   gpio-reserved-ranges:
36   "-state$":
38       - $ref: "#/$defs/qcom-sdx55-tlmm-state"
39       - patternProperties:
40           "-pins$":
41             $ref: "#/$defs/qcom-sdx55-tlmm-state"
45   qcom-sdx55-tlmm-state:
50     $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
59             - pattern: "^gpio([0-9]|[1-9][0-9]|10[0-7])$"
60             - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data ]
96       - pins
99   - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
102   - compatible
103   - reg
108   - |
109     #include <dt-bindings/interrupt-controller/arm-gic.h>
110     tlmm: pinctrl@1f00000 {
111         compatible = "qcom,sdx55-pinctrl";
113         gpio-controller;
114         #gpio-cells = <2>;
115         gpio-ranges = <&tlmm 0 0 108>;
116         interrupt-controller;
117         #interrupt-cells = <2>;
120         serial-state {
123             drive-strength = <8>;
124             bias-disable;