bindings/phy/samsung%2Cusb3-drd-phy.yaml

1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/samsung,usb3-drd-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Krzysztof Kozlowski <krzk@kernel.org>
11   - Marek Szyprowski <m.szyprowski@samsung.com>
12   - Sylwester Nawrocki <s.nawrocki@samsung.com>
15   For samsung,exynos5250-usbdrd-phy and samsung,exynos5420-usbdrd-phy
18     0 - UTMI+ type phy,
19     1 - PIPE3 type phy.
28       - samsung,exynos5250-usbdrd-phy
29       - samsung,exynos5420-usbdrd-phy
30       - samsung,exynos5433-usbdrd-phy
31       - samsung,exynos7-usbdrd-phy
32       - samsung,exynos850-usbdrd-phy
38   clock-names:
43         - Main PHY clock (same as USB DRD controller i.e. DWC3 IP clock), used
45         - PHY reference clock (usually crystal clock), used for PHY operations,
46           associated by phy name. It is used to determine bit values for clock
50   "#phy-cells":
62   samsung,pmu-syscon:
67   vbus-supply:
71   vbus-boost-supply:
76   - compatible
77   - clocks
78   - clock-names
79   - "#phy-cells"
80   - reg
81   - samsung,pmu-syscon
84   - if:
89               - samsung,exynos5433-usbdrd-phy
90               - samsung,exynos7-usbdrd-phy
96         clock-names:
98             - const: phy
99             - const: ref
100             - const: phy_utmi
101             - const: phy_pipe
102             - const: itp
108         clock-names:
110             - const: phy
111             - const: ref
116   - |
117     #include <dt-bindings/clock/exynos5420.h>
120         compatible = "samsung,exynos5420-usbdrd-phy";
122         #phy-cells = <1>;
123         clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>;
124         clock-names = "phy", "ref";
125         samsung,pmu-syscon = <&pmu_system_controller>;
126         vbus-supply = <&usb300_vbus_reg>;