bindings/phy/rockchip%2Cpcie3-phy.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/rockchip,pcie3-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Heiko Stuebner <heiko@sntech.de>
15       - rockchip,rk3568-pcie3-phy
16       - rockchip,rk3588-pcie3-phy
25   clock-names:
29   data-lanes:
32       (controller-number +1 )
33     $ref: /schemas/types.yaml#/definitions/uint32-array
40   "#phy-cells":
46   reset-names:
49   rockchip,phy-grf:
53   rockchip,pipe-grf:
58   - compatible
59   - reg
60   - rockchip,phy-grf
61   - "#phy-cells"
64   - if:
68             - rockchip,rk3588-pcie3-phy
73         clock-names:
75             - const: pclk
81         clock-names:
83             - const: refclk_m
84             - const: refclk_n
85             - const: pclk
90   - |
91     #include <dt-bindings/clock/rk3568-cru.h>
93       compatible = "rockchip,rk3568-pcie3-phy";
95       #phy-cells = <0>;
98                <&cru PCLK_PCIE30PHY>;
99       clock-names = "refclk_m", "refclk_n", "pclk";
100       resets = <&cru SRST_PCIE30PHY>;
101       reset-names = "phy";
102       rockchip,phy-grf = <&pcie30_phy_grf>;