bindings/phy/qcom%2Cipq8074-qmp-pcie-phy.yaml

1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,ipq8074-qmp-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm QMP PHY controller (PCIe, IPQ8074)
10   - Vinod Koul <vkoul@kernel.org>
13   QMP PHY controller supports physical layer functionality for a number of
19       - qcom,ipq6018-qmp-pcie-phy
20       - qcom,ipq8074-qmp-gen3-pcie-phy
21       - qcom,ipq8074-qmp-pcie-phy
25       - description: serdes
30   clock-names:
32       - const: aux
33       - const: cfg_ahb
34       - const: pipe
39   reset-names:
41       - const: phy
42       - const: common
44   "#clock-cells":
47   clock-output-names:
50   "#phy-cells":
54   - compatible
55   - reg
56   - clocks
57   - clock-names
58   - resets
59   - reset-names
60   - "#clock-cells"
61   - clock-output-names
62   - "#phy-cells"
67   - |
68     #include <dt-bindings/clock/qcom,gcc-ipq6018.h>
69     #include <dt-bindings/reset/qcom,gcc-ipq6018.h>
71     phy@84000 {
72         compatible = "qcom,ipq6018-qmp-pcie-phy";
78         clock-names = "aux",
82         clock-output-names = "gcc_pcie0_pipe_clk_src";
83         #clock-cells = <0>;
85         #phy-cells = <0>;
89         reset-names = "phy",