Lines Matching full:xusb

4 $id: http://devicetree.org/schemas/phy/nvidia,tegra210-xusb-padctl.yaml#
7 title: NVIDIA Tegra210 XUSB pad controller
14   The Tegra XUSB pad controller manages a set of I/O lanes (with differential
23   or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
30   Pads will be represented as children of the top-level XUSB pad controller
35   The Tegra hardware documentation refers to the connection between the XUSB
36   pad controller and the XUSB controller as "ports". This is confusing since
45     const: nvidia,tegra210-xusb-padctl
56       - description: XUSB pad controller interrupt
80       subnodes, one for each of the pads exposed by the XUSB pad controller.
117                     enum: [ snps, xusb, uart ]
129                     enum: [ snps, xusb, uart ]
141                     enum: [ snps, xusb, uart ]
153                     enum: [ snps, xusb, uart ]
181                     enum: [ snps, xusb ]
193                     enum: [ snps, xusb ]
341       subnodes, one for each of the ports exposed by the XUSB pad controller.
618         compatible = "nvidia,tegra210-xusb-padctl";
636                         nvidia,function = "xusb";
641                         nvidia,function = "xusb";
646                         nvidia,function = "xusb";
651                         nvidia,function = "xusb";