bindings/phy/mediatek%2Cdsi-phy.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/phy/mediatek,dsi-phy.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11   - Chun-Kuang Hu <chunkuang.hu@kernel.org>
12   - Philipp Zabel <p.zabel@pengutronix.de>
13   - Chunfeng Yun <chunfeng.yun@mediatek.com>
15 description: The MIPI DSI PHY supports up to 4-lane output.
19     pattern: "^dsi-phy@[0-9a-f]+$"
23       - items:
24           - enum:
25               - mediatek,mt7623-mipi-tx
26           - const: mediatek,mt2701-mipi-tx
27       - items:
28           - enum:
29               - mediatek,mt6795-mipi-tx
30           - const: mediatek,mt8173-mipi-tx
31       - items:
32           - enum:
33               - mediatek,mt8365-mipi-tx
34           - const: mediatek,mt8183-mipi-tx
35       - const: mediatek,mt2701-mipi-tx
36       - const: mediatek,mt8173-mipi-tx
37       - const: mediatek,mt8183-mipi-tx
44       - description: PLL reference clock
46   clock-output-names:
49   "#phy-cells":
52   "#clock-cells":
55   nvmem-cells:
57     description: A phandle to the calibration data provided by a nvmem device,
60   nvmem-cell-names:
62       - const: calibration-data
64   drive-strength-microamp:
72   - compatible
73   - reg
74   - clocks
75   - clock-output-names
76   - "#phy-cells"
77   - "#clock-cells"
82   - |
83     #include <dt-bindings/clock/mt8173-clk.h>
84     dsi-phy@10215000 {
85         compatible = "mediatek,mt8173-mipi-tx";
88         clock-output-names = "mipi_tx0_pll";
89         drive-strength-microamp = <4000>;
90         nvmem-cells = <&mipi_tx_calibration>;
91         nvmem-cell-names = "calibration-data";
92         #clock-cells = <0>;
93         #phy-cells = <0>;