bindings/pci/xlnx%2Cnwl-pcie.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/xlnx,nwl-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx NWL PCIe Root Port Bridge
10   - Thippeswamy Havalige <thippeswamy.havalige@amd.com>
13   - $ref: /schemas/pci/pci-bus.yaml#
14   - $ref: /schemas/interrupt-controller/msi-controller.yaml#
18     const: xlnx,nwl-pcie-2.11
22       - description: PCIe bridge registers location.
23       - description: PCIe Controller registers location.
24       - description: PCIe Configuration space region.
26   reg-names:
28       - const: breg
29       - const: pcireg
30       - const: cfg
34       - description: interrupt asserted when miscellaneous interrupt is received
35       - description: unused interrupt(dummy)
36       - description: interrupt asserted when a legacy interrupt is received
37       - description: msi1 interrupt asserted when an MSI is received
38       - description: msi0 interrupt asserted when an MSI is received
40   interrupt-names:
42       - const: misc
43       - const: dummy
44       - const: intx
45       - const: msi1
46       - const: msi0
48   interrupt-map-mask:
50       - const: 0
51       - const: 0
52       - const: 0
53       - const: 7
55   "#interrupt-cells":
58   msi-parent:
61   interrupt-map:
64   power-domains:
70   dma-coherent:
77   legacy-interrupt-controller:
81       "#address-cells":
84       "#interrupt-cells":
87       "interrupt-controller": true
90       - "#address-cells"
91       - "#interrupt-cells"
92       - interrupt-controller
97   - compatible
98   - reg
99   - reg-names
100   - interrupts
101   - "#interrupt-cells"
102   - interrupt-map
103   - interrupt-map-mask
104   - msi-controller
105   - power-domains
110   - |
111     #include <dt-bindings/interrupt-controller/arm-gic.h>
112     #include <dt-bindings/interrupt-controller/irq.h>
113     #include <dt-bindings/power/xlnx-zynqmp-power.h>
115         #address-cells = <2>;
116         #size-cells = <2>;
117         nwl_pcie: pcie@fd0e0000 {
118             compatible = "xlnx,nwl-pcie-2.11";
122             reg-names = "breg", "pcireg", "cfg";
125             #address-cells = <3>;
126             #size-cells = <2>;
127             #interrupt-cells = <1>;
128             msi-controller;
130             interrupt-parent = <&gic>;
134             interrupt-names = "misc", "dummy", "intx", "msi1", "msi0";
135             interrupt-map-mask = <0x0 0x0 0x0 0x7>;
136             interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,
140             msi-parent = <&nwl_pcie>;
141             power-domains = <&zynqmp_firmware PD_PCIE>;
143             pcie_intc: legacy-interrupt-controller {
144                 interrupt-controller;
145                 #address-cells = <0>;
146                 #interrupt-cells = <1>;