bindings/pci/ti%2Cj721e-pci-host.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: http://devicetree.org/schemas/pci/ti,j721e-pci-host.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: TI J721E PCI Host (PCIe Wrapper)
11   - Kishon Vijay Abraham I <kishon@ti.com>
14   - $ref: cdns-pcie-host.yaml#
19       - const: ti,j721e-pcie-host
20       - description: PCIe controller in AM64
22           - const: ti,am64-pcie-host
23           - const: ti,j721e-pcie-host
24       - description: PCIe controller in J7200
26           - const: ti,j7200-pcie-host
27           - const: ti,j721e-pcie-host
32   reg-names:
34       - const: intd_cfg
35       - const: user_cfg
36       - const: reg
37       - const: cfg
39   ti,syscon-pcie-ctrl:
40     $ref: /schemas/types.yaml#/definitions/phandle-array
42       - items:
43           - description: Phandle to the SYSCON entry
44           - description: pcie_ctrl register offset within SYSCON
45     description: Specifier for configuring PCIe mode and link speed.
47   power-domains:
54       clock-specifier to represent input to the PCIe for 1 item.
57   clock-names:
60       - const: fck
61       - const: pcie_refclk
63   dma-coherent: true
65   vendor-id:
68   device-id:
70       - 0xb00d
71       - 0xb00f
72       - 0xb010
73       - 0xb013
75   msi-map: true
80   interrupt-names:
82       - const: link_state
84   interrupt-controller:
89       interrupt-controller: true
91       '#interrupt-cells':
98   - compatible
99   - reg
100   - reg-names
101   - ti,syscon-pcie-ctrl
102   - max-link-speed
103   - num-lanes
104   - power-domains
105   - clocks
106   - clock-names
107   - vendor-id
108   - device-id
109   - msi-map
110   - dma-ranges
111   - ranges
112   - reset-gpios
113   - phys
114   - phy-names
119   - |
120     #include <dt-bindings/soc/ti,sci_pm_domain.h>
121     #include <dt-bindings/gpio/gpio.h>
124         #address-cells = <2>;
125         #size-cells = <2>;
127         pcie0_rc: pcie@2900000 {
128             compatible = "ti,j721e-pcie-host";
133             reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
134             ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x4070>;
135             max-link-speed = <3>;
136             num-lanes = <2>;
137             power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
139             clock-names = "fck";
141             #address-cells = <3>;
142             #size-cells = <2>;
143             bus-range = <0x0 0xf>;
144             vendor-id = <0x104c>;
145             device-id = <0xb00d>;
146             msi-map = <0x0 &gic_its 0x0 0x10000>;
147             dma-coherent;
148             reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>;
150             phy-names = "pcie-phy";
153             dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;