Lines Matching +full:max +full:- +full:speed
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: http://devicetree.org/schemas/pci/ti,j721e-pci-ep.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Kishon Vijay Abraham I <kishon@ti.com>
14 - $ref: cdns-pcie-ep.yaml#
19 - const: ti,j721e-pcie-ep
20 - description: PCIe EP controller in AM64
22 - const: ti,am64-pcie-ep
23 - const: ti,j721e-pcie-ep
24 - description: PCIe EP controller in J7200
26 - const: ti,j7200-pcie-ep
27 - const: ti,j721e-pcie-ep
32 reg-names:
34 - const: intd_cfg
35 - const: user_cfg
36 - const: reg
37 - const: mem
39 ti,syscon-pcie-ctrl:
40 $ref: /schemas/types.yaml#/definitions/phandle-array
42 - items:
43 - description: Phandle to the SYSCON entry
44 - description: pcie_ctrl register offset within SYSCON
45 description: Specifier for configuring PCIe mode and link speed.
47 power-domains:
52 description: clock-specifier to represent input to the PCIe
54 clock-names:
56 - const: fck
58 dma-coherent:
64 interrupt-names:
66 - const: link_state
69 - compatible
70 - reg
71 - reg-names
72 - ti,syscon-pcie-ctrl
73 - max-link-speed
74 - num-lanes
75 - power-domains
76 - clocks
77 - clock-names
78 - max-functions
79 - phys
80 - phy-names
85 - |
86 #include <dt-bindings/soc/ti,sci_pm_domain.h>
89 #address-cells = <2>;
90 #size-cells = <2>;
92 pcie0_ep: pcie-ep@d000000 {
93 compatible = "ti,j721e-pcie-ep";
98 reg-names = "intd_cfg", "user_cfg", "reg", "mem";
99 ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x4070>;
100 max-link-speed = <3>;
101 num-lanes = <2>;
102 power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
104 clock-names = "fck";
105 max-functions = /bits/ 8 <6>;
106 dma-coherent;
108 phy-names = "pcie-phy";