bindings/nvmem/imx-ocotp.yaml

1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/nvmem/imx-ocotp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX On-Chip OTP Controller (OCOTP)
10   - Anson Huang <Anson.Huang@nxp.com>
13   This binding represents the on-chip eFuse OTP controller found on
18   - $ref: nvmem.yaml#
23       - items:
24           - enum:
25               - fsl,imx6q-ocotp
26               - fsl,imx6sl-ocotp
27               - fsl,imx6sx-ocotp
28               - fsl,imx6ul-ocotp
29               - fsl,imx6ull-ocotp
30               - fsl,imx7d-ocotp
31               - fsl,imx6sll-ocotp
32               - fsl,imx7ulp-ocotp
33               - fsl,imx8mq-ocotp
34               - fsl,imx8mm-ocotp
35               - fsl,imx93-ocotp
36           - const: syscon
37       - items:
38           - enum:
39               - fsl,imx8mn-ocotp
40               # i.MX8MP not really compatible with fsl,imx8mm-ocotp, however
41               # the code for getting SoC revision depends on fsl,imx8mm-ocotp
43               - fsl,imx8mp-ocotp
44           - const: fsl,imx8mm-ocotp
45           - const: syscon
54   - "#address-cells"
55   - "#size-cells"
56   - compatible
57   - reg
62   - |
63     #include <dt-bindings/clock/imx6sx-clock.h>
66         #address-cells = <1>;
67         #size-cells = <1>;
68         compatible = "fsl,imx6sx-ocotp", "syscon";
72         cpu_speed_grade: speed-grade@10 {
80         tempmon_temp_grade: temp-grade@20 {