Lines Matching full:dp83867

5 $id: http://devicetree.org/schemas/net/ti,dp83867.yaml#
8 title: TI DP83867 ethernet PHY
17   The DP83867 device is a robust, low power, fully featured Physical Layer
21   The DP83867 is designed for easy implementation of 10/100/1000 Mbps Ethernet
64        Transmitt FIFO depth see dt-bindings/net/ti-dp83867.h for values
69        Receive FIFO depth see dt-bindings/net/ti-dp83867.h for values
74       Muxing option for CLK_OUT pin.  See dt-bindings/net/ti-dp83867.h
81       RGMII Receive Clock Delay - see dt-bindings/net/ti-dp83867.h
88       RGMII Transmit Clock Delay - see dt-bindings/net/ti-dp83867.h
100   ti,dp83867-rxctrl-strap-quirk:
118       Transmitt FIFO depth- see dt-bindings/net/ti-dp83867.h for applicable
128     #include <dt-bindings/net/ti-dp83867.h>