Lines Matching +full:rmii +full:- +full:refclk +full:- +full:in
1 # SPDX-License-Identifier: GPL-2.0+
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
18 - $ref: ethernet-phy.yaml#
21 "^ethernet-phy@[0-9a-f]+$":
34 nxp,rmii-refclk-in:
38 in RMII mode. This clock signal is provided by the PHY and is
45 interface reference clock input when RMII mode enabled.
47 reference clock output when RMII mode enabled.
51 - reg
56 - |
58 #address-cells = <1>;
59 #size-cells = <0>;
61 tja1101_phy0: ethernet-phy@4 {
63 nxp,rmii-refclk-in;
66 - |
68 #address-cells = <1>;
69 #size-cells = <0>;
71 tja1102_phy0: ethernet-phy@4 {
73 #address-cells = <1>;
74 #size-cells = <0>;
76 tja1102_phy1: ethernet-phy@5 {