Lines Matching +full:mt7622 +full:- +full:pcie +full:- +full:mirror
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Bianconi <lorenzo@kernel.org>
11 - Felix Fietkau <nbd@nbd.name>
20 - mediatek,mt2701-eth
21 - mediatek,mt7623-eth
22 - mediatek,mt7621-eth
23 - mediatek,mt7622-eth
24 - mediatek,mt7629-eth
25 - mediatek,mt7981-eth
26 - mediatek,mt7986-eth
27 - mediatek,mt7988-eth
28 - ralink,rt5350-eth
34 clock-names: true
40 power-domains:
46 reset-names:
48 - const: fe
49 - const: gmac
50 - const: ppe
57 cci-control-port: true
72 $ref: /schemas/types.yaml#/definitions/phandle-array
82 $ref: /schemas/types.yaml#/definitions/phandle-array
90 mediatek,wed-pcie:
93 Phandle to the mediatek wed-pcie controller.
95 dma-coherent: true
97 mdio-bus:
101 "#address-cells":
104 "#size-cells":
108 - $ref: ethernet-controller.yaml#
109 - if:
114 - mediatek,mt2701-eth
115 - mediatek,mt7623-eth
125 clock-names:
127 - const: ethif
128 - const: esw
129 - const: gp1
130 - const: gp2
142 mediatek,wed-pcie: false
144 - if:
149 - mediatek,mt7621-eth
159 clock-names:
161 - const: ethif
162 - const: fe
168 mediatek,wed-pcie: false
170 - if:
174 const: mediatek,mt7622-eth
184 clock-names:
186 - const: ethif
187 - const: esw
188 - const: gp0
189 - const: gp1
190 - const: gp2
191 - const: sgmii_tx250m
192 - const: sgmii_rx250m
193 - const: sgmii_cdr_ref
194 - const: sgmii_cdr_fb
195 - const: sgmii_ck
196 - const: eth2pll
204 mediatek,pcie-mirror:
207 Phandle to the mediatek pcie-mirror controller.
209 mediatek,wed-pcie: false
211 - if:
215 const: mediatek,mt7629-eth
225 clock-names:
227 - const: ethif
228 - const: sgmiitop
229 - const: esw
230 - const: gp0
231 - const: gp1
232 - const: gp2
233 - const: fe
234 - const: sgmii_tx250m
235 - const: sgmii_rx250m
236 - const: sgmii_cdr_ref
237 - const: sgmii_cdr_fb
238 - const: sgmii2_tx250m
239 - const: sgmii2_rx250m
240 - const: sgmii2_cdr_ref
241 - const: sgmii2_cdr_fb
242 - const: sgmii_ck
243 - const: eth2pll
251 mediatek,wed-pcie: false
253 - if:
257 const: mediatek,mt7981-eth
267 clock-names:
269 - const: fe
270 - const: gp2
271 - const: gp1
272 - const: wocpu0
273 - const: sgmii_ck
274 - const: sgmii_tx250m
275 - const: sgmii_rx250m
276 - const: sgmii_cdr_ref
277 - const: sgmii_cdr_fb
278 - const: sgmii2_tx250m
279 - const: sgmii2_rx250m
280 - const: sgmii2_cdr_ref
281 - const: sgmii2_cdr_fb
282 - const: netsys0
283 - const: netsys1
291 - if:
295 const: mediatek,mt7986-eth
305 clock-names:
307 - const: fe
308 - const: gp2
309 - const: gp1
310 - const: wocpu1
311 - const: wocpu0
312 - const: sgmii_tx250m
313 - const: sgmii_rx250m
314 - const: sgmii_cdr_ref
315 - const: sgmii_cdr_fb
316 - const: sgmii2_tx250m
317 - const: sgmii2_rx250m
318 - const: sgmii2_cdr_ref
319 - const: sgmii2_cdr_fb
320 - const: netsys0
321 - const: netsys1
329 - if:
333 const: mediatek,mt7988-eth
343 clock-names:
345 - const: crypto
346 - const: fe
347 - const: gp2
348 - const: gp1
349 - const: gp3
350 - const: ethwarp_wocpu2
351 - const: ethwarp_wocpu1
352 - const: ethwarp_wocpu0
353 - const: esw
354 - const: top_eth_gmii_sel
355 - const: top_eth_refck_50m_sel
356 - const: top_eth_sys_200m_sel
357 - const: top_eth_sys_sel
358 - const: top_eth_xgmii_sel
359 - const: top_eth_mii_sel
360 - const: top_netsys_sel
361 - const: top_netsys_500m_sel
362 - const: top_netsys_pao_2x_sel
363 - const: top_netsys_sync_250m_sel
364 - const: top_netsys_ppefb_250m_sel
365 - const: top_netsys_warp_sel
366 - const: xgp1
367 - const: xgp2
368 - const: xgp3
371 "^mac@[0-1]$":
375 - $ref: ethernet-controller.yaml#
380 const: mediatek,eth-mac
386 - reg
387 - compatible
390 - compatible
391 - reg
392 - interrupts
393 - clocks
394 - clock-names
395 - mediatek,ethsys
400 - |
401 #include <dt-bindings/interrupt-controller/arm-gic.h>
402 #include <dt-bindings/interrupt-controller/irq.h>
403 #include <dt-bindings/clock/mt7622-clk.h>
404 #include <dt-bindings/power/mt7622-power.h>
407 #address-cells = <2>;
408 #size-cells = <2>;
411 compatible = "mediatek,mt7622-eth";
427 clock-names = "ethif", "esw", "gp0", "gp1", "gp2",
431 power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;
434 cci-control-port = <&cci_control2>;
435 mediatek,pcie-mirror = <&pcie_mirror>;
437 dma-coherent;
439 #address-cells = <1>;
440 #size-cells = <0>;
442 mdio0: mdio-bus {
443 #address-cells = <1>;
444 #size-cells = <0>;
446 phy0: ethernet-phy@0 {
450 phy1: ethernet-phy@1 {
456 compatible = "mediatek,eth-mac";
457 phy-mode = "rgmii";
458 phy-handle = <&phy0>;
463 compatible = "mediatek,eth-mac";
464 phy-mode = "rgmii";
465 phy-handle = <&phy1>;
471 - |
472 #include <dt-bindings/interrupt-controller/arm-gic.h>
473 #include <dt-bindings/interrupt-controller/irq.h>
474 #include <dt-bindings/clock/mt7622-clk.h>
477 #address-cells = <2>;
478 #size-cells = <2>;
491 compatible = "mediatek,mt7986-eth";
512 clock-names = "fe", "gp2", "gp1", "wocpu1", "wocpu0",
520 assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
522 assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>,
525 #address-cells = <1>;
526 #size-cells = <0>;
528 mdio: mdio-bus {
529 #address-cells = <1>;
530 #size-cells = <0>;
532 phy5: ethernet-phy@0 {
533 compatible = "ethernet-phy-id67c9.de0a";
534 phy-mode = "2500base-x";
535 reset-gpios = <&pio 6 1>;
536 reset-deassert-us = <20000>;
540 phy6: ethernet-phy@1 {
541 compatible = "ethernet-phy-id67c9.de0a";
542 phy-mode = "2500base-x";
548 compatible = "mediatek,eth-mac";
549 phy-mode = "2500base-x";
550 phy-handle = <&phy5>;
555 compatible = "mediatek,eth-mac";
556 phy-mode = "2500base-x";
557 phy-handle = <&phy6>;