bindings/net/hisilicon-hix5hd2-gmac.txt

1 Hisilicon hix5hd2 gmac controller
4 - compatible: should contain one of the following SoC strings:
5 	* "hisilicon,hix5hd2-gmac"
6 	* "hisilicon,hi3798cv200-gmac"
7 	* "hisilicon,hi3516a-gmac"
9 	* "hisilicon,hisi-gmac-v1"
10 	* "hisilicon,hisi-gmac-v2"
11   The version v1 includes SoCs hix5hd2.
13 - reg: specifies base physical address(s) and size of the device registers.
16 - interrupts: should contain the MAC interrupt.
17 - #address-cells: must be <1>.
18 - #size-cells: must be <0>.
19 - phy-mode: see ethernet.txt [1].
20 - phy-handle: see ethernet.txt [1].
21 - clocks: clock phandle and specifier pair.
22 - clock-names: contain the clock name "mac_core"(required) and "mac_ifc"(optional).
23 - resets: should contain the phandle to the MAC core reset signal(optional),
26 - reset-names: contain the reset signal name "mac_core"(optional),
28 - hisilicon,phy-reset-delays-us: triplet of delays if PHY reset signal given.
29 	The 1st cell is reset pre-delay in micro seconds.
31 	The 3rd cell is reset post-delay in micro seconds.
36 - PHY subnode: inherits from phy binding [2]
43 		compatible = "hisilicon,hi3798cv200-gmac", "hisilicon,hisi-gmac-v2";
46 		#address-cells = <1>;
47 		#size-cells = <0>;
48 		phy-mode = "rgmii";
49 		phy-handle = <&phy2>;
50 		mac-address = [00 00 00 00 00 00];
52 		clock-names = "mac_core", "mac_ifc";
54 		reset-names = "mac_core", "mac_ifc", "phy";
55 		hisilicon,phy-reset-delays-us = <10000 10000 30000>;
57 		phy2: ethernet-phy@2 {