Lines Matching +full:phy +full:- +full:output +full:- +full:reference +full:- +full:clock
1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Guo <shawnguo@kernel.org>
11 - Wei Fang <wei.fang@nxp.com>
12 - NXP Linux Team <linux-imx@nxp.com>
15 - $ref: ethernet-controller.yaml#
20 - enum:
21 - fsl,imx25-fec
22 - fsl,imx27-fec
23 - fsl,imx28-fec
24 - fsl,imx6q-fec
25 - fsl,mvf600-fec
26 - fsl,s32v234-fec
27 - items:
28 - enum:
29 - fsl,imx53-fec
30 - fsl,imx6sl-fec
31 - const: fsl,imx25-fec
32 - items:
33 - enum:
34 - fsl,imx35-fec
35 - fsl,imx51-fec
36 - const: fsl,imx27-fec
37 - items:
38 - enum:
39 - fsl,imx6ul-fec
40 - fsl,imx6sx-fec
41 - const: fsl,imx6q-fec
42 - items:
43 - enum:
44 - fsl,imx7d-fec
45 - const: fsl,imx6sx-fec
46 - items:
47 - const: fsl,imx8mq-fec
48 - const: fsl,imx6sx-fec
49 - items:
50 - enum:
51 - fsl,imx8mm-fec
52 - fsl,imx8mn-fec
53 - fsl,imx8mp-fec
54 - fsl,imx93-fec
55 - const: fsl,imx8mq-fec
56 - const: fsl,imx6sx-fec
57 - items:
58 - const: fsl,imx8qm-fec
59 - const: fsl,imx6sx-fec
60 - items:
61 - enum:
62 - fsl,imx8qxp-fec
63 - const: fsl,imx8qm-fec
64 - const: fsl,imx6sx-fec
65 - items:
66 - enum:
67 - fsl,imx8ulp-fec
68 - const: fsl,imx6ul-fec
69 - const: fsl,imx6q-fec
78 interrupt-names:
80 - items:
81 - const: int0
82 - items:
83 - const: int0
84 - const: pps
85 - items:
86 - const: int0
87 - const: int1
88 - const: int2
89 - items:
90 - const: int0
91 - const: int1
92 - const: int2
93 - const: pps
100 The "ahb", for MAC ipg_clk, ipg_clk_mac that are bus clock.
101 The "ptp"(option), for IEEE1588 timer clock that requires the clock.
102 The "enet_clk_ref"(option), for MAC transmit/receiver reference clock like
103 RGMII TXC clock or RMII reference clock. It depends on board design,
104 the clock is required if RGMII TXC and RMII reference clock source from
106 The "enet_out"(option), output clock for external device, like supply clock
107 for PHY. The clock is required if PHY clock source from SOC.
108 The "enet_2x_txclk"(option), for RGMII sampling clock which fixed at 250Mhz.
109 The clock is required if SoC RGMII enable clock delay.
111 clock-names:
116 - ipg
117 - ahb
118 - ptp
119 - enet_clk_ref
120 - enet_out
121 - enet_2x_txclk
123 phy-mode: true
125 phy-handle: true
127 fixed-link: true
129 local-mac-address: true
131 mac-address: true
133 nvmem-cells: true
135 nvmem-cell-names: true
137 tx-internal-delay-ps:
140 rx-internal-delay-ps:
143 phy-supply:
145 Regulator that powers the Ethernet PHY.
147 power-domains:
150 fsl,num-tx-queues:
153 The property is valid for enet-avb IP, which supports hw multi queues.
157 fsl,num-rx-queues:
160 The property is valid for enet-avb IP, which supports hw multi queues.
164 fsl,magic-packet:
169 fsl,err006687-workaround-present:
175 fsl,stop-mode:
176 $ref: /schemas/types.yaml#/definitions/phandle-array
178 - items:
179 - description: phandle to general purpose register node
180 - description: the gpr register offset for ENET stop request
181 - description: the gpr bit offset for ENET stop request
185 fsl,pps-channel:
196 Specifies the mdio bus in the FEC, used as a container for phy nodes.
199 # To avoid these, create a phy node according to ethernet-phy.yaml in the same
200 # directory, and point the FEC's "phy-handle" property to it. Then use
201 # the phy's reset binding, again described by ethernet-phy.yaml.
203 phy-reset-gpios:
206 Should specify the gpio for phy reset.
208 phy-reset-duration:
213 "phy-reset-gpios" is available. Missing the property will have the
217 phy-reset-active-high:
222 "phy-reset-gpios" property is reversed (H=reset state, L=operation state).
224 phy-reset-post-delay:
228 Post reset delay in milliseconds. If present then a delay of phy-reset-post-delay
229 milliseconds will be observed after the phy-reset-gpios has been toggled.
234 - compatible
235 - reg
236 - interrupts
239 # least undocumented properties. However, PHY may have a deprecated option to
240 # place PHY OF properties in the MAC node, such as Micrel PHY, and we can find
245 - |
247 compatible = "fsl,imx51-fec", "fsl,imx27-fec";
250 phy-mode = "mii";
251 phy-reset-gpios = <&gpio2 14 0>;
252 phy-supply = <®_fec_supply>;
256 compatible = "fsl,imx51-fec", "fsl,imx27-fec";
259 phy-mode = "mii";
260 phy-reset-gpios = <&gpio2 14 0>;
261 phy-supply = <®_fec_supply>;
262 phy-handle = <ðphy0>;
265 #address-cells = <1>;
266 #size-cells = <0>;
268 ethphy0: ethernet-phy@0 {
269 compatible = "ethernet-phy-ieee802.3-c22";