Lines Matching full:nand
7 title: Broadcom STB NAND Controller
14 The Broadcom Set-Top Box NAND controller supports low-level access to raw NAND
25 -- Additional SoC-specific NAND controller properties --
27 The NAND controller is integrated differently on the variety of SoCs on which
29 bits with which to control the 8 exposed NAND interrupts, as well as hardware
33 interesting ways, sometimes with registers that lump multiple NAND-related
37 register resources within the NAND controller node above.
56 - description: BCM63138 SoC-specific NAND controller
58 - const: brcm,nand-bcm63138
63 - description: iProc SoC-specific NAND controller
65 - const: brcm,nand-iproc
68 - description: BCM63168 SoC-specific NAND controller
70 - const: brcm,nand-bcm63168
71 - const: brcm,nand-bcm6368
83 enum: [ nand, flash-dma, flash-edu, nand-cache, nand-int-base, iproc-idm, iproc-ext ]
88 - description: NAND CTLRDY interrupt
101 description: reference to the clock for the NAND controller
104 const: nand
106 brcm,nand-has-wp:
115 "^nand@[a-f0-9]$":
117 $ref: raw-nand-chip.yaml
122 nand-ecc-step-size:
125 brcm,nand-oob-sector-size:
133 the flash geometry (particularly the NAND page
135 from NAND, the boot controller has only a limited
143 - $ref: nand-controller.yaml#
148 const: brcm,nand-bcm63138
153 - const: nand
154 - const: nand-int-base
159 const: brcm,nand-bcm6368
164 - const: nand
165 - const: nand-int-base
166 - const: nand-cache
171 const: brcm,nand-iproc
176 - const: nand
196 nand-controller@f0442800 {
200 reg-names = "nand", "flash-dma";
208 nand@1 {
211 nand-on-flash-bbt;
212 nand-ecc-strength = <12>;
213 nand-ecc-step-size = <512>;
220 nand-controller@10000200 {
221 compatible = "brcm,nand-bcm63168", "brcm,nand-bcm6368",
226 reg-names = "nand", "nand-int-base", "nand-cache";
230 clock-names = "nand";
235 nand@0 {
238 nand-on-flash-bbt;
239 nand-ecc-strength = <1>;
240 nand-ecc-step-size = <512>;