bindings/mmc/synopsys-dw-mshc.yaml

1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/synopsys-dw-mshc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Ulf Hansson <ulf.hansson@linaro.org>
16       - altr,socfpga-dw-mshc
17       - img,pistachio-dw-mshc
18       - snps,dw-mshc
31       bus interface unit clock and the card interface unit clock.
33   clock-names:
35       - const: biu
36       - const: ciu
38   altr,sysmgr-syscon:
39     $ref: /schemas/types.yaml#/definitions/phandle-array
41       - items:
42           - description: phandle to the sysmgr node
43           - description: register offset that controls the SDMMC clock phase
44           - description: register shift for the smplsel(drive in) setting
47       that contains the SDMMC clock-phase control register. The first value is
49       SDMMC clock phase register, and the 3rd value is the bit shift for the
53   - $ref: synopsys-dw-mshc-common.yaml#
55   - if:
59             const: altr,socfpga-dw-mshc
62         altr,sysmgr-syscon: true
65         altr,sysmgr-syscon: false
68   - compatible
69   - reg
70   - interrupts
71   - clocks
72   - clock-names
77   - |
79       compatible = "snps,dw-mshc";
82       clocks = <&clock 351>, <&clock 132>;
83       clock-names = "biu", "ciu";
85       dma-names = "rx-tx";
87       reset-names = "reset";
88       vmmc-supply = <&buck8>;
89       #address-cells = <1>;
90       #size-cells = <0>;
91       broken-cd;
92       bus-width = <8>;
93       cap-mmc-highspeed;
94       cap-sd-highspeed;
95       card-detect-delay = <200>;
96       max-frequency = <200000000>;
97       clock-frequency = <400000000>;
98       data-addr = <0x200>;
99       fifo-depth = <0x80>;
100       fifo-watermark-aligned;