Lines Matching +full:mt8192 +full:- +full:pericfg
1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/mtk-sd.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chaotian Jing <chaotian.jing@mediatek.com>
11 - Wenbin Mei <wenbin.mei@mediatek.com>
16 - enum:
17 - mediatek,mt2701-mmc
18 - mediatek,mt2712-mmc
19 - mediatek,mt6779-mmc
20 - mediatek,mt6795-mmc
21 - mediatek,mt7620-mmc
22 - mediatek,mt7622-mmc
23 - mediatek,mt7986-mmc
24 - mediatek,mt8135-mmc
25 - mediatek,mt8173-mmc
26 - mediatek,mt8183-mmc
27 - mediatek,mt8516-mmc
28 - items:
29 - const: mediatek,mt7623-mmc
30 - const: mediatek,mt2701-mmc
31 - items:
32 - enum:
33 - mediatek,mt8186-mmc
34 - mediatek,mt8188-mmc
35 - mediatek,mt8192-mmc
36 - mediatek,mt8195-mmc
37 - mediatek,mt8365-mmc
38 - const: mediatek,mt8183-mmc
43 - description: base register (required).
44 - description: top base register (required for MT8183).
52 clock-names:
58 Should at least contain MSDC GIC interrupt. To support SDIO in-band wakeup, an extended
63 interrupt-names:
65 - const: msdc
66 - const: sdio_wakeup
68 pinctrl-names:
70 Should at least contain default and state_uhs. To support SDIO in-band wakeup, dat1 pin
75 - const: default
76 - const: state_uhs
77 - const: state_eint
79 pinctrl-0:
84 pinctrl-1:
89 pinctrl-2:
94 hs400-ds-delay:
101 mediatek,hs200-cmd-int-delay:
110 mediatek,hs400-cmd-int-delay:
119 mediatek,hs400-cmd-resp-sel-rising:
126 mediatek,hs400-ds-dly3:
138 mediatek,latch-ck:
141 Some SoCs do not support enhance_rx, need set correct latch-ck to avoid
144 applied to compatible "mediatek,mt2701-mmc".
151 reset-names:
155 - compatible
156 - reg
157 - interrupts
158 - clocks
159 - clock-names
160 - pinctrl-names
161 - pinctrl-0
162 - pinctrl-1
163 - vmmc-supply
164 - vqmmc-supply
167 - $ref: mmc-controller.yaml#
168 - if:
172 - mediatek,mt2701-mmc
173 - mediatek,mt6779-mmc
174 - mediatek,mt6795-mmc
175 - mediatek,mt7620-mmc
176 - mediatek,mt7622-mmc
177 - mediatek,mt7623-mmc
178 - mediatek,mt8135-mmc
179 - mediatek,mt8173-mmc
180 - mediatek,mt8183-mmc
181 - mediatek,mt8186-mmc
182 - mediatek,mt8188-mmc
183 - mediatek,mt8195-mmc
184 - mediatek,mt8516-mmc
190 - description: source clock
191 - description: HCLK which used for host
192 - description: independent source clock gate
193 clock-names:
196 - const: source
197 - const: hclk
198 - const: source_cg
200 - if:
204 const: mediatek,mt2712-mmc
210 - description: source clock
211 - description: HCLK which used for host
212 - description: independent source clock gate
213 - description: bus clock used for internal register access (required for MSDC0/3).
214 clock-names:
217 - const: source
218 - const: hclk
219 - const: source_cg
220 - const: bus_clk
222 - if:
226 const: mediatek,mt8183-mmc
232 - if:
237 - mediatek,mt7986-mmc
243 - description: source clock
244 - description: HCLK which used for host
245 - description: independent source clock gate
246 - description: bus clock used for internal register access (required for MSDC0/3).
247 - description: msdc subsys clock gate
248 clock-names:
251 - const: source
252 - const: hclk
253 - const: source_cg
254 - const: bus_clk
255 - const: sys_cg
257 - if:
261 - mediatek,mt8186-mmc
262 - mediatek,mt8188-mmc
263 - mediatek,mt8195-mmc
268 - description: source clock
269 - description: HCLK which used for host
270 - description: independent source clock gate
271 - description: crypto clock used for data encrypt/decrypt (optional)
272 clock-names:
274 - const: source
275 - const: hclk
276 - const: source_cg
277 - const: crypto
279 - if:
283 const: mediatek,mt8192-mmc
288 - description: source clock
289 - description: HCLK which used for host
290 - description: independent source clock gate
291 - description: msdc subsys clock gate
292 - description: peripheral bus clock gate
293 - description: AXI bus clock gate
294 - description: AHB bus clock gate
295 clock-names:
297 - const: source
298 - const: hclk
299 - const: source_cg
300 - const: sys_cg
301 - const: pclk_cg
302 - const: axi_cg
303 - const: ahb_cg
308 - |
309 #include <dt-bindings/interrupt-controller/irq.h>
310 #include <dt-bindings/interrupt-controller/arm-gic.h>
311 #include <dt-bindings/clock/mt8173-clk.h>
313 compatible = "mediatek,mt8173-mmc";
316 vmmc-supply = <&mt6397_vemc_3v3_reg>;
317 vqmmc-supply = <&mt6397_vio18_reg>;
318 clocks = <&pericfg CLK_PERI_MSDC30_0>,
320 clock-names = "source", "hclk";
321 pinctrl-names = "default", "state_uhs";
322 pinctrl-0 = <&mmc0_pins_default>;
323 pinctrl-1 = <&mmc0_pins_uhs>;
324 assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>;
325 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
326 hs400-ds-delay = <0x14015>;
327 mediatek,hs200-cmd-int-delay = <26>;
328 mediatek,hs400-cmd-int-delay = <14>;
329 mediatek,hs400-cmd-resp-sel-rising;
333 compatible = "mediatek,mt8173-mmc";
335 clock-names = "source", "hclk";
336 clocks = <&pericfg CLK_PERI_MSDC30_3>,
338 interrupt-names = "msdc", "sdio_wakeup";
339 interrupts-extended = <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_LOW 0>,
341 pinctrl-names = "default", "state_uhs", "state_eint";
342 pinctrl-0 = <&mmc2_pins_default>;
343 pinctrl-1 = <&mmc2_pins_uhs>;
344 pinctrl-2 = <&mmc2_pins_eint>;
345 bus-width = <4>;
346 max-frequency = <200000000>;
347 cap-sd-highspeed;
348 sd-uhs-sdr104;
349 keep-power-in-suspend;
350 wakeup-source;
351 cap-sdio-irq;
352 no-mmc;
353 no-sd;
354 non-removable;
355 vmmc-supply = <&sdio_fixed_3v3>;
356 vqmmc-supply = <&mt6397_vgp3_reg>;
357 mmc-pwrseq = <&wifi_pwrseq>;