Lines Matching refs:LPC
8 title: Aspeed Low Pin Count (LPC) Bus Controller
15 The LPC bus is a means to bridge a host CPU to a number of low-bandwidth
17 primary use case of the Aspeed LPC controller is as a slave on the bus
21 The LPC controller is represented as a multi-function device to account for the
26 * An LPC Host Interface Controller manages functions exposed to the host such
27 as LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART
34 Additionally the state of the LPC controller influences the pinmux
65 The LPC Host Interface Controller manages functions exposed to the host such as
66 LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART management
85 description: handle to memory reservation for the LPC to AHB mapping region
89 …description: The SPI flash controller containing the flash to be exposed over the LPC to AHB mappi…
101 state of the LPC bus. Some systems may chose to modify this configuration
126 The LPC snoop interface allows the BMC to listen on and record the data
127 bytes written by the Host to the targeted LPC I/O pots.
145 description: The LPC I/O ports to snoop
154 description: The UART routing control under LPC register space