bindings/memory-controllers/rockchip%2Crk3399-dmc.yaml

91       srpd_lite_idle * 1024 DFI clock cycles. This parameter is for LPDDR4
130       When the DRAM type is DDR3, this parameter defines the ODT disable
138       When the DRAM type is DDR3, this parameter defines the DRAM side drive
146       When the DRAM type is DDR3, this parameter defines the DRAM side ODT
154       When the DRAM type is DDR3, this parameter defines the phy side CA line
162       When the DRAM type is DDR3, this parameter defines the PHY side DQ line
170       When the DRAM type is DDR3, this parameter defines the PHY side ODT
178       When the DRAM type is LPDDR3, this parameter defines then ODT disable
186       When the DRAM type is LPDDR3, this parameter defines the DRAM side drive
194       When the DRAM type is LPDDR3, this parameter defines the DRAM side ODT
202       When the DRAM type is LPDDR3, this parameter defines the PHY side CA line
210       When the DRAM type is LPDDR3, this parameter defines the PHY side DQ line
218       When dram type is LPDDR3, this parameter define the phy side odt
225       When the DRAM type is LPDDR4, this parameter defines the ODT disable
233       When the DRAM type is LPDDR4, this parameter defines the DRAM side drive
241       When the DRAM type is LPDDR4, this parameter defines the DRAM side ODT on
249       When the DRAM type is LPDDR4, this parameter defines the DRAM side ODT on
257       When the DRAM type is LPDDR4, this parameter defines the PHY side CA line
265       When the DRAM type is LPDDR4, this parameter defines the PHY side clock
273       When the DRAM type is LPDDR4, this parameter defines the PHY side DQ line
281       When the DRAM type is LPDDR4, this parameter defines the PHY side ODT
308       srpd_lite_idle nanoseconds. This parameter is for LPDDR4 only.