bindings/memory-controllers/rockchip%2Crk3399-dmc.yaml

71       SR_IDLE * 1024 DFI clock cycles (DFI clocks freq is half of DRAM clock).
100       self-refresh mode. The controller, pi, PHY and DRAM clock will be gated
130       When the DRAM type is DDR3, this parameter defines the ODT disable
132       the ODT on the DRAM side and controller side are both disabled.
138       When the DRAM type is DDR3, this parameter defines the DRAM side drive
146       When the DRAM type is DDR3, this parameter defines the DRAM side ODT
154       When the DRAM type is DDR3, this parameter defines the phy side CA line
162       When the DRAM type is DDR3, this parameter defines the PHY side DQ line
170       When the DRAM type is DDR3, this parameter defines the PHY side ODT
178       When the DRAM type is LPDDR3, this parameter defines then ODT disable
180       ODT on the DRAM side and controller side are both disabled.
186       When the DRAM type is LPDDR3, this parameter defines the DRAM side drive
194       When the DRAM type is LPDDR3, this parameter defines the DRAM side ODT
202       When the DRAM type is LPDDR3, this parameter defines the PHY side CA line
210       When the DRAM type is LPDDR3, this parameter defines the PHY side DQ line
225       When the DRAM type is LPDDR4, this parameter defines the ODT disable
227       the ODT on the DRAM side and controller side are both disabled.
233       When the DRAM type is LPDDR4, this parameter defines the DRAM side drive
241       When the DRAM type is LPDDR4, this parameter defines the DRAM side ODT on
249       When the DRAM type is LPDDR4, this parameter defines the DRAM side ODT on
257       When the DRAM type is LPDDR4, this parameter defines the PHY side CA line
265       When the DRAM type is LPDDR4, this parameter defines the PHY side clock
273       When the DRAM type is LPDDR4, this parameter defines the PHY side DQ line
281       When the DRAM type is LPDDR4, this parameter defines the PHY side ODT
313       self-refresh mode. The controller, pi, PHY and DRAM clock will be gated