Lines Matching refs:memory
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra186-mc.yaml#
14 The NVIDIA Tegra186 SoC features a 128 bit memory controller that is split
16 handles memory requests for 40-bit virtual addresses from internal clients
17 and arbitrates among them to allocate memory bandwidth.
19 Up to 15 GiB of physical memory can be supported. Security features such as
27 pattern: "^memory-controller@[0-9a-f]+$"
62 "^external-memory-controller@[0-9a-f]+$":
64 The bulk of the work involved in controlling the external memory
67 which the external memory is clocked and a remote procedure call that
88 - description: external memory clock
150 description: 5 memory controller channels and 1 for stream-id registers
169 description: 17 memory controller channels and 1 for stream-id registers
200 description: 17 memory controller channels and 1 for stream-id registers
242 memory-controller@2c00000 {
259 * Memory clients have access to all 40 bits that the memory
264 external-memory-controller@2c60000 {