memory-controllers/ddr/jedec%2Clpddr3.yaml

45       CKE minimum pulse width (HIGH and LOW pulse width) in terms of number
46       of clock cycles.
53       SELF REFRESH) in terms of number of clock cycles.
59       DQS output data access time from CK_t/CK_c in terms of number of clock
66       Four-bank activate window in terms of number of clock cycles.
72       Mode register set command delay in terms of number of clock cycles.
78       Additional READ-to-READ delay in chip-to-chip cases in terms of number
79       of clock cycles.
85       Row active time in terms of number of clock cycles.
91       ACTIVATE-to-ACTIVATE command period in terms of number of clock cycles.
97       RAS-to-CAS delay in terms of number of clock cycles.
103       Refresh Cycle time in terms of number of clock cycles.
109      READ data latency in terms of number of clock cycles.
115       Row precharge time (all banks) in terms of number of clock cycles.
121       Row precharge time (single banks) in terms of number of clock cycles.
127       Active bank A to active bank B in terms of number of clock cycles.
133       Internal READ to PRECHARGE command delay in terms of number of clock
140       Additional WRITE-to-WRITE delay in chip-to-chip cases in terms of number
141       of clock cycles.
147       WRITE data latency in terms of number of clock cycles.
153       WRITE recovery time in terms of number of clock cycles.
159       Internal WRITE-to-READ command delay in terms of number of clock cycles.
165       Exit power-down to next valid command delay in terms of number of clock
172       SELF REFRESH exit to next valid command delay in terms of number of clock
180       Each timing node provides AC timing parameters of the device for a given