bindings/media/mediatek%2Cmdp3-rdma.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/mediatek,mdp3-rdma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Matthias Brugger <matthias.bgg@gmail.com>
11   - Moudy Ho <moudy.ho@mediatek.com>
24       - const: mediatek,mt8183-mdp3-rdma
29   mediatek,gce-client-reg:
30     $ref: /schemas/types.yaml#/definitions/phandle-array
33         - description: phandle of GCE
34         - description: GCE subsys id
35         - description: register offset
36         - description: register size
39       a client defined in the header include/dt-bindings/gce/<chip>-gce.h.
41   mediatek,gce-events:
45       include/dt-bindings/gce/<chip>-gce.h of each chips.
46     $ref: /schemas/types.yaml#/definitions/uint32-array
48   power-domains:
53       - description: RDMA clock
54       - description: RSZ clock
61       - description: used for 1st data pipe from RDMA
62       - description: used for 2nd data pipe from RDMA
64   '#dma-cells':
68   - compatible
69   - reg
70   - mediatek,gce-client-reg
71   - mediatek,gce-events
72   - power-domains
73   - clocks
74   - iommus
75   - mboxes
76   - '#dma-cells'
81   - |
82     #include <dt-bindings/clock/mt8183-clk.h>
83     #include <dt-bindings/gce/mt8183-gce.h>
84     #include <dt-bindings/power/mt8183-power.h>
85     #include <dt-bindings/memory/mt8183-larb-port.h>
87     dma-controller@14001000 {
88         compatible = "mediatek,mt8183-mdp3-rdma";
90         mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>;
91         mediatek,gce-events = <CMDQ_EVENT_MDP_RDMA0_SOF>,
93         power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
99         #dma-cells = <1>;