bindings/media/cdns%2Ccsi2rx.yaml

1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cadence MIPI-CSI2 RX controller
10   - Maxime Ripard <mripard@kernel.org>
13   The Cadence MIPI-CSI2 RX controller is a CSI-2 bridge supporting up to 4 CSI
19       - enum:
20           - starfive,jh7110-csi2rx
21       - const: cdns,csi2rx
28       - description: CSI2Rx system clock
29       - description: Gated Register bank clock for APB interface
30       - description: pixel Clock for Stream interface 0
31       - description: pixel Clock for Stream interface 1
32       - description: pixel Clock for Stream interface 2
33       - description: pixel Clock for Stream interface 3
35   clock-names:
37       - const: sys_clk
38       - const: p_clk
39       - const: pixel_if0_clk
40       - const: pixel_if1_clk
41       - const: pixel_if2_clk
42       - const: pixel_if3_clk
46       - description: CSI2Rx system reset
47       - description: Gated Register bank reset for APB interface
48       - description: pixel reset for Stream interface 0
49       - description: pixel reset for Stream interface 1
50       - description: pixel reset for Stream interface 2
51       - description: pixel reset for Stream interface 3
53   reset-names:
55       - const: sys
56       - const: reg_bank
57       - const: pixel_if0
58       - const: pixel_if1
59       - const: pixel_if2
60       - const: pixel_if3
64     description: MIPI D-PHY
66   phy-names:
68       - const: dphy
75         $ref: /schemas/graph.yaml#/$defs/port-base
78           Input port node, single endpoint describing the CSI-2 transmitter.
82             $ref: video-interfaces.yaml#
86               bus-type:
89               clock-lanes:
92               data-lanes:
99               - data-lanes
122       - port@0
125   - compatible
126   - reg
127   - clocks
128   - clock-names
129   - ports
134   - |
136         compatible = "starfive,jh7110-csi2rx", "cdns,csi2rx";
141         clock-names = "sys_clk", "p_clk",
147         reset-names = "sys", "reg_bank",
151         phy-names = "dphy";
154                 #address-cells = <1>;
155                 #size-cells = <0>;
161                         remote-endpoint = <&sensor_out_csi2rx>;
162                         clock-lanes = <0>;
163                         data-lanes = <1 2>;
171                         remote-endpoint = <&grabber0_in_csi2rx>;
179                         remote-endpoint = <&grabber1_in_csi2rx>;
187                         remote-endpoint = <&grabber2_in_csi2rx>;
195                         remote-endpoint = <&grabber3_in_csi2rx>;