bindings/mailbox/fsl%2Cmu.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Dong Aisheng <aisheng.dong@nxp.com>
16   for one processor to signal the other processor using interrupts.
22   registers (Processor A-facing, Processor B-facing).
27       - const: fsl,imx6sx-mu
28       - const: fsl,imx7ulp-mu
29       - const: fsl,imx8ulp-mu
30       - const: fsl,imx8-mu-scu
31       - const: fsl,imx8-mu-seco
32       - const: fsl,imx93-mu-s4
33       - const: fsl,imx8ulp-mu-s4
34       - items:
35           - const: fsl,imx93-mu
36           - const: fsl,imx8ulp-mu
37       - items:
38           - enum:
39               - fsl,imx7s-mu
40               - fsl,imx8mq-mu
41               - fsl,imx8mm-mu
42               - fsl,imx8mn-mu
43               - fsl,imx8mp-mu
44               - fsl,imx8qm-mu
45               - fsl,imx8qxp-mu
46           - const: fsl,imx6sx-mu
47       - description: To communicate with i.MX8 SCU with fast IPC
49           - const: fsl,imx8-mu-scu
50           - enum:
51               - fsl,imx8qm-mu
52               - fsl,imx8qxp-mu
53           - const: fsl,imx6sx-mu
58   interrupts:
62   interrupt-names:
65       - const: tx
66       - const: rx
68   "#mbox-cells":
70       <&phandle type channel>
72       type      : Channel type
73       channel   : Channel number
76       has 4 channels except RST channel which only has 1 channel.
79       0 - TX channel with 32bit transmit register and IRQ transmit
81       1 - RX channel with 32bit receive register and IRQ support
82       2 - TX doorbell channel. Without own register and no ACK support.
83       3 - RX doorbell channel.
84       4 - RST channel
90   fsl,mu-side-b:
94   power-domains:
98   - compatible
99   - reg
100   - interrupts
101   - "#mbox-cells"
104   - if:
108             - fsl,imx93-mu-s4
111         interrupt-names:
113         interrupts:
118         interrupts:
122           - interrupt-names
127   - |
128     #include <dt-bindings/interrupt-controller/arm-gic.h>
131         compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
133         interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
134         #mbox-cells = <2>;