Lines Matching full:smmu
4 $id: http://devicetree.org/schemas/iommu/arm,smmu.yaml#
18 The SMMU may also raise interrupts in response to various fault
26 - description: Qcom SoCs implementing "arm,smmu-v2"
29 - qcom,msm8996-smmu-v2
30 - qcom,msm8998-smmu-v2
31 - qcom,sdm630-smmu-v2
32 - qcom,sm6375-smmu-v2
33 - const: qcom,smmu-v2
35 - description: Qcom SoCs implementing "qcom,smmu-500" and "arm,mmu-500"
38 - qcom,qcm2290-smmu-500
39 - qcom,qdu1000-smmu-500
40 - qcom,sa8775p-smmu-500
41 - qcom,sc7180-smmu-500
42 - qcom,sc7280-smmu-500
43 - qcom,sc8180x-smmu-500
44 - qcom,sc8280xp-smmu-500
45 - qcom,sdm670-smmu-500
46 - qcom,sdm845-smmu-500
47 - qcom,sdx55-smmu-500
48 - qcom,sdx65-smmu-500
49 - qcom,sdx75-smmu-500
50 - qcom,sm6115-smmu-500
51 - qcom,sm6125-smmu-500
52 - qcom,sm6350-smmu-500
53 - qcom,sm6375-smmu-500
54 - qcom,sm8150-smmu-500
55 - qcom,sm8250-smmu-500
56 - qcom,sm8350-smmu-500
57 - qcom,sm8450-smmu-500
58 - qcom,sm8550-smmu-500
59 - const: qcom,smmu-500
67 - qcom,qcm2290-smmu-500
68 - qcom,sc7180-smmu-500
69 - qcom,sc7280-smmu-500
70 - qcom,sc8180x-smmu-500
71 - qcom,sc8280xp-smmu-500
72 - qcom,sdm845-smmu-500
73 - qcom,sm6115-smmu-500
74 - qcom,sm6350-smmu-500
75 - qcom,sm6375-smmu-500
76 - qcom,sm8150-smmu-500
77 - qcom,sm8250-smmu-500
78 - qcom,sm8350-smmu-500
79 - qcom,sm8450-smmu-500
81 - description: Qcom Adreno GPUs implementing "qcom,smmu-500" and "arm,mmu-500"
84 - qcom,sa8775p-smmu-500
85 - qcom,sc7280-smmu-500
86 - qcom,sc8280xp-smmu-500
87 - qcom,sm6115-smmu-500
88 - qcom,sm6125-smmu-500
89 - qcom,sm8150-smmu-500
90 - qcom,sm8250-smmu-500
91 - qcom,sm8350-smmu-500
92 - const: qcom,adreno-smmu
93 - const: qcom,smmu-500
100 - qcom,sc7280-smmu-500
101 - qcom,sm8150-smmu-500
102 - qcom,sm8250-smmu-500
103 - const: qcom,adreno-smmu
105 - description: Qcom Adreno GPUs implementing "arm,smmu-v2"
108 - qcom,msm8996-smmu-v2
109 - qcom,sc7180-smmu-v2
110 - qcom,sdm630-smmu-v2
111 - qcom,sdm845-smmu-v2
112 - qcom,sm6350-smmu-v2
113 - const: qcom,adreno-smmu
114 - const: qcom,smmu-v2
117 - const: qcom,sdm845-smmu-v2
118 - const: qcom,smmu-v2
121 - const: marvell,ap806-smmu-500
129 - nvidia,tegra186-smmu
130 - nvidia,tegra194-smmu
131 - nvidia,tegra234-smmu
132 - const: nvidia,smmu-500
135 - const: arm,smmu-v2
140 - const: arm,smmu-v1
142 - arm,smmu-v1
143 - arm,smmu-v2
147 - cavium,smmu-v2
164 by that device into the relevant SMMU.
177 interrupts, specified in order of their indexing by the SMMU.
185 Present if page table walks made by the SMMU are cache coherent with the
188 NOTE: this only applies to the SMMU itself, not masters connected
189 upstream of the SMMU.
191 calxeda,smmu-secure-config-access:
195 access to SMMU configuration registers. In this case non-secure aliases of
196 secure registers have to be used during SMMU configuration.
226 client IDs to ARM SMMU stream IDs.
248 - nvidia,tegra186-smmu
249 - nvidia,tegra194-smmu
250 - nvidia,tegra234-smmu
272 - qcom,msm8998-smmu-v2
273 - qcom,sdm630-smmu-v2
283 the smmu ptw
292 - description: interface clock required to access smmu's registers
300 - const: iface-smmu
301 - const: bus-smmu
306 - description: interface clock required to access smmu's registers
308 - description: bus clock required for the smmu ptw
315 - qcom,sm6375-smmu-v2
325 the smmu ptw
334 - description: interface clock required to access smmu's registers
342 - const: iface-smmu
344 - const: bus-smmu
349 - description: interface clock required to access smmu's registers
352 - description: bus clock required for the smmu ptw
359 - qcom,msm8996-smmu-v2
360 - qcom,sc7180-smmu-v2
361 - qcom,sdm845-smmu-v2
372 the smmu ptw
373 - description: interface clock required to access smmu's registers
381 - qcom,sa8775p-smmu-500
382 - qcom,sc7280-smmu-500
383 - qcom,sc8280xp-smmu-500
401 - description: GPU hlos1_vote_GPU smmu clock
411 - qcom,sm6350-smmu-v2
412 - qcom,sm8150-smmu-500
413 - qcom,sm8250-smmu-500
426 the smmu ptw
427 - description: interface clock required to access smmu's registers
435 - qcom,sm6115-smmu-500
436 - qcom,sm6125-smmu-500
437 - const: qcom,adreno-smmu
438 - const: qcom,smmu-500
451 - description: Voter clock required for HLOS SMMU access
460 - cavium,smmu-v2
461 - marvell,ap806-smmu-500
462 - nvidia,smmu-500
463 - qcom,qcm2290-smmu-500
464 - qcom,qdu1000-smmu-500
465 - qcom,sc7180-smmu-500
466 - qcom,sc8180x-smmu-500
467 - qcom,sdm670-smmu-500
468 - qcom,sdm845-smmu-500
469 - qcom,sdx55-smmu-500
470 - qcom,sdx65-smmu-500
471 - qcom,sm6350-smmu-500
472 - qcom,sm6375-smmu-500
473 - qcom,sm8350-smmu-500
474 - qcom,sm8450-smmu-500
475 - qcom,sm8550-smmu-500
485 const: qcom,sm6375-smmu-500
503 /* SMMU with stream matching or stream indexing */
505 compatible = "arm,smmu-v1";
524 /* SMMU with stream matching */
526 compatible = "arm,smmu-v1";
552 compatible = "arm,mmu-500", "arm,smmu-v2";
568 ID each, but may master through multiple SMMU TBUs */
575 /* Qcom's arm,smmu-v2 implementation */
579 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";