bindings/interrupt-controller/qcom%2Cpdc.yaml

1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/qcom,pdc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Bjorn Andersson <bjorn.andersson@linaro.org>
14   Power Domain Controller (PDC) that is on always-on domain. In addition to
17   well detect interrupts when the GIC is non-operational.
28       - enum:
29           - qcom,qdu1000-pdc
30           - qcom,sa8775p-pdc
31           - qcom,sc7180-pdc
32           - qcom,sc7280-pdc
33           - qcom,sc8280xp-pdc
34           - qcom,sdm670-pdc
35           - qcom,sdm845-pdc
36           - qcom,sdx55-pdc
37           - qcom,sdx65-pdc
38           - qcom,sm6350-pdc
39           - qcom,sm8150-pdc
40           - qcom,sm8250-pdc
41           - qcom,sm8350-pdc
42           - qcom,sm8450-pdc
43       - const: qcom,pdc
48       - description: PDC base register region
49       - description: Edge or Level config register for SPI interrupts
51   '#interrupt-cells':
54   interrupt-controller: true
56   qcom,pdc-ranges:
57     $ref: /schemas/types.yaml#/definitions/uint32-matrix
62         - description: starting PDC port
63         - description: GIC hwirq number for the PDC port
64         - description: number of interrupts in sequence
71   - compatible
72   - reg
73   - '#interrupt-cells'
74   - interrupt-controller
75   - qcom,pdc-ranges
80   - |
81     #include <dt-bindings/interrupt-controller/irq.h>
83     pdc: interrupt-controller@b220000 {
84         compatible = "qcom,sdm845-pdc", "qcom,pdc";
86         qcom,pdc-ranges = <0 512 94>, <94 641 15>, <115 662 7>;
87         #interrupt-cells = <2>;
88         interrupt-parent = <&intc>;
89         interrupt-controller;
92     wake-device {
93         interrupts-extended = <&pdc 2 IRQ_TYPE_LEVEL_HIGH>;