bindings/interrupt-controller/qcom%2Cmpm.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/qcom,mpm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Shawn Guo <shawn.guo@linaro.org>
13   Qualcomm Technologies Inc. SoCs based on the RPM architecture have a
14   MSM Power Manager (MPM) that is in always-on domain. In addition to managing
21   - $ref: /schemas/interrupt-controller.yaml#
26       - const: qcom,mpm
31       Specifies the base address and size of vMPM registers in RPM MSG RAM.
36       Specify the IRQ used by RPM to wakeup APSS.
41       Specify the mailbox used to notify RPM for writing vMPM registers.
43   interrupt-controller: true
45   '#interrupt-cells':
51   qcom,mpm-pin-count:
56   qcom,mpm-pin-map:
59     $ref: /schemas/types.yaml#/definitions/uint32-matrix
62         - description: MPM pin number
63         - description: GIC SPI number for the MPM pin
65   '#power-domain-cells':
69   - compatible
70   - reg
71   - interrupts
72   - mboxes
73   - interrupt-controller
74   - '#interrupt-cells'
75   - qcom,mpm-pin-count
76   - qcom,mpm-pin-map
81   - |
82     #include <dt-bindings/interrupt-controller/arm-gic.h>
83     mpm: interrupt-controller@45f01b8 {
88         interrupt-controller;
89         #interrupt-cells = <2>;
90         interrupt-parent = <&intc>;
91         qcom,mpm-pin-count = <96>;
92         qcom,mpm-pin-map = <2 275>,
99         #power-domain-cells = <0>;