Lines Matching +full:ocelot +full:- +full:1

1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/mscc,ocelot-icpu-intr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microsemi Ocelot SoC ICPU Interrupt Controller
10   - Alexandre Belloni <alexandre.belloni@bootlin.com>
13   - $ref: /schemas/interrupt-controller.yaml#
16   the Microsemi Ocelot interrupt controller that is part of the
23       - enum:
24           - mscc,jaguar2-icpu-intr
25           - mscc,luton-icpu-intr
26           - mscc,ocelot-icpu-intr
27           - mscc,serval-icpu-intr
30   '#interrupt-cells':
31     const: 1
33   '#address-cells':
36   interrupt-controller: true
39     maxItems: 1
42     maxItems: 1
45   - compatible
46   - '#interrupt-cells'
47   - '#address-cells'
48   - interrupt-controller
49   - reg
54   - |
55     intc: interrupt-controller@70000070 {
56         compatible = "mscc,ocelot-icpu-intr";
58         #interrupt-cells = <1>;
59         #address-cells = <0>;
60         interrupt-controller;
61         interrupt-parent = <&cpuintc>;