iio/adc/xilinx-xadc.txt

4 as the UltraScale/UltraScale+ System Monitor.
14 The Xilinx System Monitor is an ADC that is found in the UltraScale and
15 UltraScale+ FPGAs from Xilinx. The System Monitor provides a DRP interface for
17 System Monitor through an AXI interface in the FPGA fabric. This IP core is
18 called the Xilinx System Management Wizard. This document describes the bindings
22 	- compatible: Should be one of
23 		* "xlnx,zynq-xadc-1.00.a": When using the ZYNQ device
25 		* "xlnx,axi-xadc-1.00.a": When using the axi-xadc pcore to
27 		* "xlnx,system-management-wiz-1.3": When using the
28 		  Xilinx System Management Wizard fabric IP core to access the
29 		  UltraScale and UltraScale+ System Monitor.
30 	- reg: Address and length of the register set for the device
31 	- interrupts: Interrupt for the XADC control interface.
32 	- clocks: When using the ZYNQ this must be the ZYNQ PCAP clock,
33 	  when using the axi-xadc or the axi-system-management-wizard this must be
37 	- xlnx,external-mux:
40 		* "single": External multiplexer mode is used with one
44 	- xlnx,external-mux-channel: Configures which pair of pins is used to
46 	  Valid values for single external multiplexer mode are:
53 		1: VAUXP[0]/VAUXN[0] - VAUXP[8]/VAUXN[8]
54 		2: VAUXP[1]/VAUXN[1] - VAUXP[9]/VAUXN[9]
56 		8: VAUXP[7]/VAUXN[7] - VAUXP[15]/VAUXN[15]
59 	  external multiplexer mode (either single or dual). If the device is
61 	- xnlx,channels: List of external channels that are connected to the ADC
63 		* #address-cells: Should be 1.
64 		* #size-cells: Should be 0.
88 		compatible = "xlnx,zynq-xadc-1.00.a";
91 		interrupt-parent = <&gic>;
95 			#address-cells = <1>;
96 			#size-cells = <0>;
110 		compatible = "xlnx,axi-xadc-1.00.a";
113 		interrupt-parent = <&gic>;
117 			#address-cells = <1>;
118 			#size-cells = <0>;
127 		compatible = "xlnx,system-management-wiz-1.3";
130 		interrupt-parent = <&gic>;
134 			#address-cells = <1>;
135 			#size-cells = <0>;