Lines Matching +full:dw +full:- +full:apb +full:- +full:gpio
1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/snps,dw-apb-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DesignWare APB GPIO controller
10 Synopsys DesignWare GPIO controllers have a configurable number of ports,
12 GPIO-controller properties as described in this bindings file.
15 - Hoan Tran <hoan@os.amperecomputing.com>
16 - Serge Semin <fancer.lancer@gmail.com>
20 pattern: "^gpio@[0-9a-f]+$"
23 const: snps,dw-apb-gpio
25 "#address-cells":
28 "#size-cells":
37 - description: APB interface clock source
38 - description: DW GPIO debounce reference clock source
40 clock-names:
43 - const: bus
44 - const: db
50 "^gpio-(port|controller)@[0-9a-f]+$":
54 const: snps,dw-apb-gpio-port
59 gpio-controller: true
61 '#gpio-cells':
64 gpio-line-names:
73 snps,nr-gpios:
74 description: The number of GPIO pins exported by the port.
86 one interrupt for each GPIO, provide a list of interrupts that
87 correspond to each of the GPIO pins.
91 interrupt-controller: true
93 '#interrupt-cells':
97 - compatible
98 - reg
99 - gpio-controller
100 - '#gpio-cells'
103 interrupt-controller: [ interrupts ]
110 - compatible
111 - reg
112 - "#address-cells"
113 - "#size-cells"
116 - |
117 gpio: gpio@20000 {
118 compatible = "snps,dw-apb-gpio";
120 #address-cells = <1>;
121 #size-cells = <0>;
123 porta: gpio-port@0 {
124 compatible = "snps,dw-apb-gpio-port";
126 gpio-controller;
127 #gpio-cells = <2>;
128 snps,nr-gpios = <8>;
129 interrupt-controller;
130 #interrupt-cells = <2>;
131 interrupt-parent = <&vic1>;
135 portb: gpio-port@1 {
136 compatible = "snps,dw-apb-gpio-port";
138 gpio-controller;
139 #gpio-cells = <2>;
140 snps,nr-gpios = <8>;