dma/ti/k3-udma.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
5 ---
6 $id: http://devicetree.org/schemas/dma/ti/k3-udma.yaml#
7 $schema: http://devicetree.org/meta-schemas/core.yaml#
9 title: Texas Instruments K3 NAVSS Unified DMA
12   - Peter Ujfalusi <peter.ujfalusi@gmail.com>
15   The UDMA-P is intended to perform similar (but significantly upgraded)
16   functions as the packet-oriented DMA used on previous SoC devices. The UDMA-P
18   The UDMA-P architecture facilitates the segmentation and reassembly of SoC DMA
29   on the Rx PSI-L interface.
31   The UDMA-P also supports acting as both a UTC and UDMA-C for its internal
32   channels. Channels in the UDMA-P can be configured to be either Packet-Based
33   or Third-Party channels on a channel by channel basis.
35   All transfers within NAVSS is done between PSI-L source and destination
37   The peripherals serviced by UDMA can be PSI-L native (sa2ul, cpsw, etc) or
38   legacy, non PSI-L native peripherals. In the later case a special, small PDMA
39   is tasked to act as a bridge between the PSI-L fabric and the legacy
46   - $ref: ../dma-controller.yaml#
47   - $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml#
50   "#dma-cells":
54       The cell is the PSI-L  thread ID of the remote (to UDMAP) end.
56       for source thread IDs (rx): 0 - 0x7fff
57       for destination thread IDs (tx): 0x8000 - 0xffff
59       Please refer to the device documentation for the PSI-L thread map and also
60       the PSI-L peripheral chapter for the correct thread ID.
62       When #dma-cells is 2, the second parameter is the channel ATYPE.
66       - ti,am654-navss-main-udmap
67       - ti,am654-navss-mcu-udmap
68       - ti,j721e-navss-main-udmap
69       - ti,j721e-navss-mcu-udmap
74   reg-names:
76       - const: gcfg
77       - const: rchanrt
78       - const: tchanrt
80   msi-parent: true
82   ti,ringacc:
86   ti,sci-rm-range-tchan:
90     $ref: /schemas/types.yaml#/definitions/uint32-array
95   ti,sci-rm-range-rchan:
99     $ref: /schemas/types.yaml#/definitions/uint32-array
104   ti,sci-rm-range-rflow:
108     $ref: /schemas/types.yaml#/definitions/uint32-array
114   - compatible
115   - "#dma-cells"
116   - reg
117   - reg-names
118   - msi-parent
119   - ti,sci
120   - ti,sci-dev-id
121   - ti,ringacc
122   - ti,sci-rm-range-tchan
123   - ti,sci-rm-range-rchan
124   - ti,sci-rm-range-rflow
128     "#dma-cells":
132     ti,udma-atype:
137     - ti,udma-atype
142   - |+
144         #address-cells = <2>;
145         #size-cells = <2>;
147         cbass_main_navss: navss@30800000 {
148             compatible = "simple-mfd";
149             #address-cells = <2>;
150             #size-cells = <2>;
151             dma-coherent;
152             dma-ranges;
155             ti,sci-dev-id = <118>;
157             main_udmap: dma-controller@31150000 {
158                 compatible = "ti,am654-navss-main-udmap";
162                 reg-names = "gcfg", "rchanrt", "tchanrt";
163                 #dma-cells = <1>;
165                 ti,ringacc = <&ringacc>;
167                 msi-parent = <&inta_main_udmass>;
170                 ti,sci-dev-id = <188>;
172                 ti,sci-rm-range-tchan = <0x1>, /* TX_HCHAN */
174                 ti,sci-rm-range-rchan = <0x4>, /* RX_HCHAN */
176                 ti,sci-rm-range-rflow = <0x6>; /* GP RFLOW */