Lines Matching +full:0 +full:x4a800000
39 for source thread IDs (rx): 0 - 0x7fff
40 for destination thread IDs (tx): 0x8000 - 0xffff
68 maximum: 0x3f
79 maximum: 0x3f
90 maximum: 0x3f
101 maximum: 0x3f
136 reg = <0x0 0x485c0000 0x0 0x100>,
137 <0x0 0x4a800000 0x0 0x20000>,
138 <0x0 0x4aa00000 0x0 0x40000>,
139 <0x0 0x4b800000 0x0 0x400000>;
147 ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */
148 <0x24>, /* CPSW_TX_CHAN */
149 <0x25>, /* SAUL_TX_0_CHAN */
150 <0x26>, /* SAUL_TX_1_CHAN */
151 <0x27>, /* ICSSG_0_TX_CHAN */
152 <0x28>; /* ICSSG_1_TX_CHAN */
153 ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */
154 <0x11>, /* RING_CPSW_TX_CHAN */
155 <0x12>, /* RING_SAUL_TX_0_CHAN */
156 <0x13>, /* RING_SAUL_TX_1_CHAN */
157 <0x14>, /* RING_ICSSG_0_TX_CHAN */
158 <0x15>; /* RING_ICSSG_1_TX_CHAN */
159 ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */
160 <0x2b>, /* CPSW_RX_CHAN */
161 <0x2d>, /* SAUL_RX_0_CHAN */
162 <0x2f>, /* SAUL_RX_1_CHAN */
163 <0x31>, /* SAUL_RX_2_CHAN */
164 <0x33>, /* SAUL_RX_3_CHAN */
165 <0x35>, /* ICSSG_0_RX_CHAN */
166 <0x37>; /* ICSSG_1_RX_CHAN */
167 ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */
168 <0x2c>, /* FLOW_CPSW_RX_CHAN */
169 <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */
170 <0x32>, /* FLOW_SAUL_RX_2/3_CHAN */
171 <0x36>, /* FLOW_ICSSG_0_RX_CHAN */
172 <0x38>; /* FLOW_ICSSG_1_RX_CHAN */