bindings/dma/snps%2Cdw-axi-dmac.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/snps,dw-axi-dmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DesignWare AXI DMA Controller
10   - Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
13   Synopsys DesignWare AXI DMA Controller DT Binding
16   - $ref: dma-controller.yaml#
21       - snps,axi-dma-1.01a
22       - intel,kmb-axi-dma
23       - starfive,jh7110-axi-dma
28       - description: Address range of the DMAC registers
29       - description: Address range of the DMAC APB registers
31   reg-names:
33       - const: axidma_ctrl_regs
34       - const: axidma_apb_regs
38       If the IP-core synthesis parameter DMAX_INTR_IO_TYPE is set to 1, this
39       will be per-channel interrupts. Otherwise, this is a single combined IRQ
46       - description: Bus Clock
47       - description: Module Clock
49   clock-names:
51       - const: core-clk
52       - const: cfgr-clk
54   '#dma-cells':
57   dma-channels:
65   snps,dma-masters:
67       Number of AXI masters supported by the hardware.
71   snps,data-width:
73       AXI data width supported by hardware.
74       (0 - 8bits, 1 - 16bits, 2 - 32bits, ..., 6 - 512bits)
81     $ref: /schemas/types.yaml#/definitions/uint32-array
85   snps,block-size:
88     $ref: /schemas/types.yaml#/definitions/uint32-array
92   snps,axi-max-burst-len:
94       Restrict master AXI burst length by value specified in this property.
95       If this property is missing the maximum AXI burst length supported by
102   - compatible
103   - reg
104   - clocks
105   - clock-names
106   - interrupts
107   - '#dma-cells'
108   - dma-channels
109   - snps,dma-masters
110   - snps,data-width
111   - snps,priority
112   - snps,block-size
119           - starfive,jh7110-axi-dma
125         - description: AXI reset line
126         - description: AHB reset line
127         - description: module reset
136   - |
137     #include <dt-bindings/interrupt-controller/arm-gic.h>
138     #include <dt-bindings/interrupt-controller/irq.h>
139     /* example with snps,dw-axi-dmac */
140     dma-controller@80000 {
141         compatible = "snps,axi-dma-1.01a";
144         clock-names = "core-clk", "cfgr-clk";
145         interrupt-parent = <&intc>;
147         #dma-cells = <1>;
148         dma-channels = <4>;
149         snps,dma-masters = <2>;
150         snps,data-width = <3>;
151         snps,block-size = <4096 4096 4096 4096>;
153         snps,axi-max-burst-len = <16>;