bindings/dma/qcom_hidma_mgmt.txt

4 memcpy and memset capabilities. It has been designed for virtualized
7 Each HIDMA HW instance consists of multiple DMA channels. These channels
9 among channels based on the priority and weight assignments.
18 - compatible: "qcom,hidma-mgmt-1.0";
19 - reg: Address range for DMA device
20 - dma-channels: Number of channels supported by this DMA controller.
21 - max-write-burst-bytes: Maximum write burst in bytes that HIDMA can
22   occupy the bus for in a single transaction. A memcpy requested is
26 - max-read-burst-bytes: Maximum read burst in bytes that HIDMA can
27   occupy the bus for in a single transaction. A memcpy request is
31 - max-write-transactions: This value is how many times a write burst is
34 - max-read-transactions: This value is how many times a read burst is
36 - channel-reset-timeout-cycles: Channel reset timeout in cycles for this SOC.
41 Sub-nodes:
43 HIDMA has one or more DMA channels that are used to move data from one
50 - compatible: must contain "qcom,hidma-1.0" for initial HW or
51   "qcom,hidma-1.1"/"qcom,hidma-1.2" for MSI capable HW.
52 - reg: Addresses for the transfer and event channel
53 - interrupts: Should contain the event interrupt
54 - desc-count: Number of asynchronous requests this channel can handle
55 - iommus: required a iommu node
58 - msi-parent : See the generic MSI binding described in
59  devicetree/bindings/interrupt-controller/msi.txt for a description of the
60  msi-parent property.
66 	hidma-mgmt@f9984000 = {
67 		compatible = "qcom,hidma-mgmt-1.0";
69 		dma-channels = <6>;
70 		max-write-burst-bytes = <1024>;
71 		max-read-burst-bytes = <1024>;
72 		max-write-transactions = <31>;
73 		max-read-transactions = <31>;
74 		channel-reset-timeout-cycles = <0x500>;
76 		hidma_24: dma-controller@5c050000 {
77 			compatible = "qcom,hidma-1.0";
81 			desc-count = <10>;
88 	hidma_24: dma-controller@5c050000 {
89 		compatible = "qcom,hidma-1.0";
93 		desc-count = <10>;