Lines Matching +full:sm8550 +full:- +full:dsi +full:- +full:ctrl
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sm8550-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SM8550 Display MDSS
10 - Neil Armstrong <neil.armstrong@linaro.org>
13 SM8550 MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like
14 DPU display controller, DSI and DP interfaces etc.
16 $ref: /schemas/display/msm/mdss-common.yaml#
20 const: qcom,sm8550-mdss
24 - description: Display MDSS AHB
25 - description: Display AHB
26 - description: Display hf AXI
27 - description: Display core
35 interconnect-names:
39 "^display-controller@[0-9a-f]+$":
43 const: qcom,sm8550-dpu
45 "^displayport-controller@[0-9a-f]+$":
50 - const: qcom,sm8550-dp
51 - const: qcom,sm8350-dp
53 "^dsi@[0-9a-f]+$":
58 - const: qcom,sm8550-dsi-ctrl
59 - const: qcom,mdss-dsi-ctrl
61 "^phy@[0-9a-f]+$":
65 const: qcom,sm8550-dsi-phy-4nm
68 - compatible
73 - |
74 #include <dt-bindings/clock/qcom,sm8550-dispcc.h>
75 #include <dt-bindings/clock/qcom,sm8550-gcc.h>
76 #include <dt-bindings/clock/qcom,rpmh.h>
77 #include <dt-bindings/interrupt-controller/arm-gic.h>
78 #include <dt-bindings/interconnect/qcom,sm8550-rpmh.h>
79 #include <dt-bindings/power/qcom,rpmhpd.h>
81 display-subsystem@ae00000 {
82 compatible = "qcom,sm8550-mdss";
84 reg-names = "mdss";
88 interconnect-names = "mdp0-mem", "mdp1-mem";
92 power-domains = <&dispcc MDSS_GDSC>;
98 clock-names = "iface", "bus", "nrt_bus", "core";
101 interrupt-controller;
102 #interrupt-cells = <1>;
106 #address-cells = <1>;
107 #size-cells = <1>;
110 display-controller@ae01000 {
111 compatible = "qcom,sm8550-dpu";
114 reg-names = "mdp", "vbif";
122 clock-names = "bus",
129 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
130 assigned-clock-rates = <19200000>;
132 operating-points-v2 = <&mdp_opp_table>;
133 power-domains = <&rpmhpd RPMHPD_MMCX>;
135 interrupt-parent = <&mdss>;
139 #address-cells = <1>;
140 #size-cells = <0>;
145 remote-endpoint = <&dsi0_in>;
152 remote-endpoint = <&dsi1_in>;
157 mdp_opp_table: opp-table {
158 compatible = "operating-points-v2";
160 opp-200000000 {
161 opp-hz = /bits/ 64 <200000000>;
162 required-opps = <&rpmhpd_opp_low_svs>;
165 opp-325000000 {
166 opp-hz = /bits/ 64 <325000000>;
167 required-opps = <&rpmhpd_opp_svs>;
170 opp-375000000 {
171 opp-hz = /bits/ 64 <375000000>;
172 required-opps = <&rpmhpd_opp_svs_l1>;
175 opp-514000000 {
176 opp-hz = /bits/ 64 <514000000>;
177 required-opps = <&rpmhpd_opp_nom>;
182 dsi@ae94000 {
183 compatible = "qcom,sm8550-dsi-ctrl", "qcom,mdss-dsi-ctrl";
185 reg-names = "dsi_ctrl";
187 interrupt-parent = <&mdss>;
196 clock-names = "byte",
203 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
205 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
207 operating-points-v2 = <&dsi_opp_table>;
208 power-domains = <&rpmhpd RPMHPD_MMCX>;
211 phy-names = "dsi";
213 #address-cells = <1>;
214 #size-cells = <0>;
217 #address-cells = <1>;
218 #size-cells = <0>;
223 remote-endpoint = <&dpu_intf1_out>;
234 dsi_opp_table: opp-table {
235 compatible = "operating-points-v2";
237 opp-187500000 {
238 opp-hz = /bits/ 64 <187500000>;
239 required-opps = <&rpmhpd_opp_low_svs>;
242 opp-300000000 {
243 opp-hz = /bits/ 64 <300000000>;
244 required-opps = <&rpmhpd_opp_svs>;
247 opp-358000000 {
248 opp-hz = /bits/ 64 <358000000>;
249 required-opps = <&rpmhpd_opp_svs_l1>;
255 compatible = "qcom,sm8550-dsi-phy-4nm";
259 reg-names = "dsi_phy",
263 #clock-cells = <1>;
264 #phy-cells = <0>;
268 clock-names = "iface", "ref";
271 dsi@ae96000 {
272 compatible = "qcom,sm8550-dsi-ctrl", "qcom,mdss-dsi-ctrl";
274 reg-names = "dsi_ctrl";
276 interrupt-parent = <&mdss>;
285 clock-names = "byte",
292 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
294 assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
296 operating-points-v2 = <&dsi_opp_table>;
297 power-domains = <&rpmhpd RPMHPD_MMCX>;
300 phy-names = "dsi";
302 #address-cells = <1>;
303 #size-cells = <0>;
306 #address-cells = <1>;
307 #size-cells = <0>;
312 remote-endpoint = <&dpu_intf2_out>;
325 compatible = "qcom,sm8550-dsi-phy-4nm";
329 reg-names = "dsi_phy",
333 #clock-cells = <1>;
334 #phy-cells = <0>;
338 clock-names = "iface", "ref";