Lines Matching +full:0 +full:x0ae95000

39   "^display-controller@[0-9a-f]+$":
45   "^displayport-controller@[0-9a-f]+$":
53   "^dsi@[0-9a-f]+$":
61   "^phy@[0-9a-f]+$":
83         reg = <0x0ae00000 0x1000>;
86         interconnects = <&mmss_noc MASTER_MDP 0 &gem_noc SLAVE_LLCC 0>,
87                         <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>;
104         iommus = <&apps_smmu 0x1c00 0x2>;
112             reg = <0x0ae01000 0x8f000>,
113                   <0x0aeb0000 0x2008>;
136             interrupts = <0>;
140                 #size-cells = <0>;
142                 port@0 {
143                     reg = <0>;
184             reg = <0x0ae94000 0x400>;
205             assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
214             #size-cells = <0>;
218                 #size-cells = <0>;
220                 port@0 {
221                     reg = <0>;
256             reg = <0x0ae95000 0x200>,
257                   <0x0ae95200 0x280>,
258                   <0x0ae95500 0x400>;
264             #phy-cells = <0>;
273             reg = <0x0ae96000 0x400>;
294             assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
303             #size-cells = <0>;
307                 #size-cells = <0>;
309                 port@0 {
310                     reg = <0>;
326             reg = <0x0ae97000 0x200>,
327                   <0x0ae97200 0x280>,
328                   <0x0ae97500 0x400>;
334             #phy-cells = <0>;