Lines Matching +full:sm8450 +full:- +full:mdss
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sm8450-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SM8450 Display MDSS
10 - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
13 SM8450 MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like
16 $ref: /schemas/display/msm/mdss-common.yaml#
20 const: qcom,sm8450-mdss
24 - description: Display AHB
25 - description: Display hf AXI
26 - description: Display sf AXI
27 - description: Display core
35 interconnect-names:
39 "^display-controller@[0-9a-f]+$":
43 const: qcom,sm8450-dpu
45 "^displayport-controller@[0-9a-f]+$":
50 - const: qcom,sm8450-dp
51 - const: qcom,sm8350-dp
53 "^dsi@[0-9a-f]+$":
58 - const: qcom,sm8450-dsi-ctrl
59 - const: qcom,mdss-dsi-ctrl
61 "^phy@[0-9a-f]+$":
65 const: qcom,sm8450-dsi-phy-5nm
68 - compatible
73 - |
74 #include <dt-bindings/clock/qcom,sm8450-dispcc.h>
75 #include <dt-bindings/clock/qcom,gcc-sm8450.h>
76 #include <dt-bindings/clock/qcom,rpmh.h>
77 #include <dt-bindings/interrupt-controller/arm-gic.h>
78 #include <dt-bindings/interconnect/qcom,sm8450.h>
79 #include <dt-bindings/power/qcom,rpmhpd.h>
81 display-subsystem@ae00000 {
82 compatible = "qcom,sm8450-mdss";
84 reg-names = "mdss";
88 interconnect-names = "mdp0-mem", "mdp1-mem";
92 power-domains = <&dispcc MDSS_GDSC>;
98 clock-names = "iface", "bus", "nrt_bus", "core";
101 interrupt-controller;
102 #interrupt-cells = <1>;
106 #address-cells = <1>;
107 #size-cells = <1>;
110 display-controller@ae01000 {
111 compatible = "qcom,sm8450-dpu";
114 reg-names = "mdp", "vbif";
122 clock-names = "bus",
129 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
130 assigned-clock-rates = <19200000>;
132 operating-points-v2 = <&mdp_opp_table>;
133 power-domains = <&rpmhpd RPMHPD_MMCX>;
135 interrupt-parent = <&mdss>;
139 #address-cells = <1>;
140 #size-cells = <0>;
145 remote-endpoint = <&dsi0_in>;
152 remote-endpoint = <&dsi1_in>;
157 mdp_opp_table: opp-table {
158 compatible = "operating-points-v2";
160 opp-172000000{
161 opp-hz = /bits/ 64 <172000000>;
162 required-opps = <&rpmhpd_opp_low_svs_d1>;
165 opp-200000000 {
166 opp-hz = /bits/ 64 <200000000>;
167 required-opps = <&rpmhpd_opp_low_svs>;
170 opp-325000000 {
171 opp-hz = /bits/ 64 <325000000>;
172 required-opps = <&rpmhpd_opp_svs>;
175 opp-375000000 {
176 opp-hz = /bits/ 64 <375000000>;
177 required-opps = <&rpmhpd_opp_svs_l1>;
180 opp-500000000 {
181 opp-hz = /bits/ 64 <500000000>;
182 required-opps = <&rpmhpd_opp_nom>;
188 compatible = "qcom,sm8450-dsi-ctrl", "qcom,mdss-dsi-ctrl";
190 reg-names = "dsi_ctrl";
192 interrupt-parent = <&mdss>;
201 clock-names = "byte",
208 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
210 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
212 operating-points-v2 = <&dsi_opp_table>;
213 power-domains = <&rpmhpd RPMHPD_MMCX>;
216 phy-names = "dsi";
218 #address-cells = <1>;
219 #size-cells = <0>;
222 #address-cells = <1>;
223 #size-cells = <0>;
228 remote-endpoint = <&dpu_intf1_out>;
239 dsi_opp_table: opp-table {
240 compatible = "operating-points-v2";
242 opp-160310000{
243 opp-hz = /bits/ 64 <160310000>;
244 required-opps = <&rpmhpd_opp_low_svs_d1>;
247 opp-187500000 {
248 opp-hz = /bits/ 64 <187500000>;
249 required-opps = <&rpmhpd_opp_low_svs>;
252 opp-300000000 {
253 opp-hz = /bits/ 64 <300000000>;
254 required-opps = <&rpmhpd_opp_svs>;
257 opp-358000000 {
258 opp-hz = /bits/ 64 <358000000>;
259 required-opps = <&rpmhpd_opp_svs_l1>;
265 compatible = "qcom,sm8450-dsi-phy-5nm";
269 reg-names = "dsi_phy",
273 #clock-cells = <1>;
274 #phy-cells = <0>;
278 clock-names = "iface", "ref";
279 vdds-supply = <&vreg_dsi_phy>;
283 compatible = "qcom,sm8450-dsi-ctrl", "qcom,mdss-dsi-ctrl";
285 reg-names = "dsi_ctrl";
287 interrupt-parent = <&mdss>;
296 clock-names = "byte",
303 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
305 assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
307 operating-points-v2 = <&dsi_opp_table>;
308 power-domains = <&rpmhpd RPMHPD_MMCX>;
311 phy-names = "dsi";
313 #address-cells = <1>;
314 #size-cells = <0>;
317 #address-cells = <1>;
318 #size-cells = <0>;
323 remote-endpoint = <&dpu_intf2_out>;
336 compatible = "qcom,sm8450-dsi-phy-5nm";
340 reg-names = "dsi_phy",
344 #clock-cells = <1>;
345 #phy-cells = <0>;
349 clock-names = "iface", "ref";
350 vdds-supply = <&vreg_dsi_phy>;