display/msm/qcom%2Csm8350-mdss.yaml

1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sm8350-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SM8350 Display MDSS
10   - Robert Foss <robert.foss@linaro.org>
13   MSM Mobile Display Subsystem(MDSS) that encapsulates sub-blocks like
16 $ref: /schemas/display/msm/mdss-common.yaml#
21       - const: qcom,sm8350-mdss
25       - description: Display AHB clock from gcc
26       - description: Display hf axi clock
27       - description: Display sf axi clock
28       - description: Display core clock
30   clock-names:
32       - const: iface
33       - const: bus
34       - const: nrt_bus
35       - const: core
43   interconnect-names:
45       - const: mdp0-mem
46       - const: mdp1-mem
49   "^display-controller@[0-9a-f]+$":
53         const: qcom,sm8350-dpu
55   "^displayport-controller@[0-9a-f]+$":
59         const: qcom,sm8350-dp
61   "^dsi@[0-9a-f]+$":
66           - const: qcom,sm8350-dsi-ctrl
67           - const: qcom,mdss-dsi-ctrl
69   "^phy@[0-9a-f]+$":
73         const: qcom,sm8350-dsi-phy-5nm
78   - |
79     #include <dt-bindings/clock/qcom,dispcc-sm8350.h>
80     #include <dt-bindings/clock/qcom,gcc-sm8350.h>
81     #include <dt-bindings/clock/qcom,rpmh.h>
82     #include <dt-bindings/interrupt-controller/arm-gic.h>
83     #include <dt-bindings/interconnect/qcom,sm8350.h>
84     #include <dt-bindings/power/qcom,rpmhpd.h>
86     display-subsystem@ae00000 {
87         compatible = "qcom,sm8350-mdss";
89         reg-names = "mdss";
93         interconnect-names = "mdp0-mem", "mdp1-mem";
95         power-domains = <&dispcc MDSS_GDSC>;
99                  <&gcc GCC_DISP_HF_AXI_CLK>,
100                  <&gcc GCC_DISP_SF_AXI_CLK>,
102         clock-names = "iface", "bus", "nrt_bus", "core";
107         interrupt-controller;
108         #interrupt-cells = <1>;
110         #address-cells = <1>;
111         #size-cells = <1>;
114         display-controller@ae01000 {
115             compatible = "qcom,sm8350-dpu";
118             reg-names = "mdp", "vbif";
120             clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
121                      <&gcc GCC_DISP_SF_AXI_CLK>,
126             clock-names = "bus",
133             assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
134             assigned-clock-rates = <19200000>;
136             operating-points-v2 = <&mdp_opp_table>;
137             power-domains = <&rpmhpd RPMHPD_MMCX>;
139             interrupt-parent = <&mdss>;
143                 #address-cells = <1>;
144                 #size-cells = <0>;
149                         remote-endpoint = <&dsi0_in>;
154             mdp_opp_table: opp-table {
155                 compatible = "operating-points-v2";
157                 opp-200000000 {
158                     opp-hz = /bits/ 64 <200000000>;
159                     required-opps = <&rpmhpd_opp_low_svs>;
162                 opp-300000000 {
163                     opp-hz = /bits/ 64 <300000000>;
164                     required-opps = <&rpmhpd_opp_svs>;
167                 opp-345000000 {
168                     opp-hz = /bits/ 64 <345000000>;
169                     required-opps = <&rpmhpd_opp_svs_l1>;
172                 opp-460000000 {
173                     opp-hz = /bits/ 64 <460000000>;
174                     required-opps = <&rpmhpd_opp_nom>;
180             compatible = "qcom,sm8350-dsi-ctrl", "qcom,mdss-dsi-ctrl";
182             reg-names = "dsi_ctrl";
184             interrupt-parent = <&mdss>;
192                      <&gcc GCC_DISP_HF_AXI_CLK>;
193             clock-names = "byte",
200             assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
202             assigned-clock-parents = <&mdss_dsi0_phy 0>,
205             operating-points-v2 = <&dsi_opp_table>;
206             power-domains = <&rpmhpd RPMHPD_MMCX>;
211              #address-cells = <1>;
212                 #size-cells = <0>;
217                         remote-endpoint = <&dpu_intf1_out>;