Lines Matching +full:0 +full:x8f000

49   "^display-controller@[0-9a-f]+$":
55   "^displayport-controller@[0-9a-f]+$":
61   "^dsi@[0-9a-f]+$":
69   "^phy@[0-9a-f]+$":
88         reg = <0x0ae00000 0x1000>;
91         interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>,
92                         <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>;
104         iommus = <&apps_smmu 0x820 0x402>;
116             reg = <0x0ae01000 0x8f000>,
117                   <0x0aeb0000 0x2008>;
140             interrupts = <0>;
144                 #size-cells = <0>;
146                 port@0 {
147                     reg = <0>;
181             reg = <0x0ae94000 0x400>;
202             assigned-clock-parents = <&mdss_dsi0_phy 0>,
212                 #size-cells = <0>;
214                 port@0 {
215                     reg = <0>;