Lines Matching +full:opp +full:- +full:300000000
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sm8250-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
14 sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
17 $ref: /schemas/display/msm/mdss-common.yaml#
21 const: qcom,sm8250-mdss
25 - description: Display AHB clock from gcc
26 - description: Display hf axi clock
27 - description: Display sf axi clock
28 - description: Display core clock
30 clock-names:
32 - const: iface
33 - const: bus
34 - const: nrt_bus
35 - const: core
43 interconnect-names:
47 "^display-controller@[0-9a-f]+$":
51 const: qcom,sm8250-dpu
53 "^dsi@[0-9a-f]+$":
58 - const: qcom,sm8250-dsi-ctrl
59 - const: qcom,mdss-dsi-ctrl
61 "^phy@[0-9a-f]+$":
65 const: qcom,dsi-phy-7nm
68 - compatible
73 - |
74 #include <dt-bindings/clock/qcom,dispcc-sm8250.h>
75 #include <dt-bindings/clock/qcom,gcc-sm8250.h>
76 #include <dt-bindings/clock/qcom,rpmh.h>
77 #include <dt-bindings/interrupt-controller/arm-gic.h>
78 #include <dt-bindings/interconnect/qcom,sm8250.h>
79 #include <dt-bindings/power/qcom,rpmhpd.h>
81 display-subsystem@ae00000 {
82 compatible = "qcom,sm8250-mdss";
84 reg-names = "mdss";
88 interconnect-names = "mdp0-mem", "mdp1-mem";
90 power-domains = <&dispcc MDSS_GDSC>;
96 clock-names = "iface", "bus", "nrt_bus", "core";
99 interrupt-controller;
100 #interrupt-cells = <1>;
104 #address-cells = <1>;
105 #size-cells = <1>;
108 display-controller@ae01000 {
109 compatible = "qcom,sm8250-dpu";
112 reg-names = "mdp", "vbif";
118 clock-names = "iface", "bus", "core", "vsync";
120 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
121 assigned-clock-rates = <19200000>;
123 operating-points-v2 = <&mdp_opp_table>;
124 power-domains = <&rpmhpd RPMHPD_MMCX>;
126 interrupt-parent = <&mdss>;
130 #address-cells = <1>;
131 #size-cells = <0>;
136 remote-endpoint = <&dsi0_in>;
143 remote-endpoint = <&dsi1_in>;
148 mdp_opp_table: opp-table {
149 compatible = "operating-points-v2";
151 opp-200000000 {
152 opp-hz = /bits/ 64 <200000000>;
153 required-opps = <&rpmhpd_opp_low_svs>;
156 opp-300000000 {
157 opp-hz = /bits/ 64 <300000000>;
158 required-opps = <&rpmhpd_opp_svs>;
161 opp-345000000 {
162 opp-hz = /bits/ 64 <345000000>;
163 required-opps = <&rpmhpd_opp_svs_l1>;
166 opp-460000000 {
167 opp-hz = /bits/ 64 <460000000>;
168 required-opps = <&rpmhpd_opp_nom>;
174 compatible = "qcom,sm8250-dsi-ctrl", "qcom,mdss-dsi-ctrl";
176 reg-names = "dsi_ctrl";
178 interrupt-parent = <&mdss>;
187 clock-names = "byte",
194 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
196 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
198 operating-points-v2 = <&dsi_opp_table>;
199 power-domains = <&rpmhpd RPMHPD_MMCX>;
202 phy-names = "dsi";
204 #address-cells = <1>;
205 #size-cells = <0>;
208 #address-cells = <1>;
209 #size-cells = <0>;
214 remote-endpoint = <&dpu_intf1_out>;
225 dsi_opp_table: opp-table {
226 compatible = "operating-points-v2";
228 opp-187500000 {
229 opp-hz = /bits/ 64 <187500000>;
230 required-opps = <&rpmhpd_opp_low_svs>;
233 opp-300000000 {
234 opp-hz = /bits/ 64 <300000000>;
235 required-opps = <&rpmhpd_opp_svs>;
238 opp-358000000 {
239 opp-hz = /bits/ 64 <358000000>;
240 required-opps = <&rpmhpd_opp_svs_l1>;
246 compatible = "qcom,dsi-phy-7nm";
250 reg-names = "dsi_phy",
254 #clock-cells = <1>;
255 #phy-cells = <0>;
259 clock-names = "iface", "ref";
260 vdds-supply = <&vreg_dsi_phy>;
264 compatible = "qcom,sm8250-dsi-ctrl", "qcom,mdss-dsi-ctrl";
266 reg-names = "dsi_ctrl";
268 interrupt-parent = <&mdss>;
277 clock-names = "byte",
284 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
286 assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
288 operating-points-v2 = <&dsi_opp_table>;
289 power-domains = <&rpmhpd RPMHPD_MMCX>;
292 phy-names = "dsi";
294 #address-cells = <1>;
295 #size-cells = <0>;
298 #address-cells = <1>;
299 #size-cells = <0>;
304 remote-endpoint = <&dpu_intf2_out>;
317 compatible = "qcom,dsi-phy-7nm";
321 reg-names = "dsi_phy",
325 #clock-cells = <1>;
326 #phy-cells = <0>;
330 clock-names = "iface", "ref";
331 vdds-supply = <&vreg_dsi_phy>;