Lines Matching +full:required +full:- +full:opps
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sm8150-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
14 sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
17 $ref: /schemas/display/msm/mdss-common.yaml#
22 - const: qcom,sm8150-mdss
26 - description: Display AHB clock from gcc
27 - description: Display hf axi clock
28 - description: Display sf axi clock
29 - description: Display core clock
31 clock-names:
33 - const: iface
34 - const: bus
35 - const: nrt_bus
36 - const: core
44 interconnect-names:
48 "^display-controller@[0-9a-f]+$":
52 const: qcom,sm8150-dpu
54 "^dsi@[0-9a-f]+$":
59 - const: qcom,sm8150-dsi-ctrl
60 - const: qcom,mdss-dsi-ctrl
62 "^phy@[0-9a-f]+$":
66 const: qcom,dsi-phy-7nm
71 - |
72 #include <dt-bindings/clock/qcom,dispcc-sm8150.h>
73 #include <dt-bindings/clock/qcom,gcc-sm8150.h>
74 #include <dt-bindings/clock/qcom,rpmh.h>
75 #include <dt-bindings/interrupt-controller/arm-gic.h>
76 #include <dt-bindings/interconnect/qcom,sm8150.h>
77 #include <dt-bindings/power/qcom-rpmpd.h>
79 display-subsystem@ae00000 {
80 compatible = "qcom,sm8150-mdss";
82 reg-names = "mdss";
86 interconnect-names = "mdp0-mem", "mdp1-mem";
88 power-domains = <&dispcc MDSS_GDSC>;
94 clock-names = "iface", "bus", "nrt_bus", "core";
97 interrupt-controller;
98 #interrupt-cells = <1>;
102 #address-cells = <1>;
103 #size-cells = <1>;
106 display-controller@ae01000 {
107 compatible = "qcom,sm8150-dpu";
110 reg-names = "mdp", "vbif";
116 clock-names = "iface", "bus", "core", "vsync";
118 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
119 assigned-clock-rates = <19200000>;
121 operating-points-v2 = <&mdp_opp_table>;
122 power-domains = <&rpmhpd SM8150_MMCX>;
124 interrupt-parent = <&mdss>;
128 #address-cells = <1>;
129 #size-cells = <0>;
134 remote-endpoint = <&dsi0_in>;
141 remote-endpoint = <&dsi1_in>;
146 mdp_opp_table: opp-table {
147 compatible = "operating-points-v2";
149 opp-171428571 {
150 opp-hz = /bits/ 64 <171428571>;
151 required-opps = <&rpmhpd_opp_low_svs>;
154 opp-300000000 {
155 opp-hz = /bits/ 64 <300000000>;
156 required-opps = <&rpmhpd_opp_svs>;
159 opp-345000000 {
160 opp-hz = /bits/ 64 <345000000>;
161 required-opps = <&rpmhpd_opp_svs_l1>;
164 opp-460000000 {
165 opp-hz = /bits/ 64 <460000000>;
166 required-opps = <&rpmhpd_opp_nom>;
172 compatible = "qcom,sm8150-dsi-ctrl", "qcom,mdss-dsi-ctrl";
174 reg-names = "dsi_ctrl";
176 interrupt-parent = <&mdss>;
185 clock-names = "byte",
192 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
194 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
196 operating-points-v2 = <&dsi_opp_table>;
197 power-domains = <&rpmhpd SM8150_MMCX>;
200 phy-names = "dsi";
202 #address-cells = <1>;
203 #size-cells = <0>;
206 #address-cells = <1>;
207 #size-cells = <0>;
212 remote-endpoint = <&dpu_intf1_out>;
223 dsi_opp_table: opp-table {
224 compatible = "operating-points-v2";
226 opp-187500000 {
227 opp-hz = /bits/ 64 <187500000>;
228 required-opps = <&rpmhpd_opp_low_svs>;
231 opp-300000000 {
232 opp-hz = /bits/ 64 <300000000>;
233 required-opps = <&rpmhpd_opp_svs>;
236 opp-358000000 {
237 opp-hz = /bits/ 64 <358000000>;
238 required-opps = <&rpmhpd_opp_svs_l1>;
244 compatible = "qcom,dsi-phy-7nm";
248 reg-names = "dsi_phy",
252 #clock-cells = <1>;
253 #phy-cells = <0>;
257 clock-names = "iface", "ref";
258 vdds-supply = <&vreg_dsi_phy>;
262 compatible = "qcom,sm8150-dsi-ctrl", "qcom,mdss-dsi-ctrl";
264 reg-names = "dsi_ctrl";
266 interrupt-parent = <&mdss>;
275 clock-names = "byte",
282 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
284 assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
286 operating-points-v2 = <&dsi_opp_table>;
287 power-domains = <&rpmhpd SM8150_MMCX>;
290 phy-names = "dsi";
292 #address-cells = <1>;
293 #size-cells = <0>;
296 #address-cells = <1>;
297 #size-cells = <0>;
302 remote-endpoint = <&dpu_intf2_out>;
315 compatible = "qcom,dsi-phy-7nm";
319 reg-names = "dsi_phy",
323 #clock-cells = <1>;
324 #phy-cells = <0>;
328 clock-names = "iface", "ref";
329 vdds-supply = <&vreg_dsi_phy>;