Lines Matching +full:0 +full:x0ae96400

48   "^display-controller@[0-9a-f]+$":
54   "^dsi@[0-9a-f]+$":
62   "^phy@[0-9a-f]+$":
81         reg = <0x0ae00000 0x1000>;
100         iommus = <&apps_smmu 0x800 0x420>;
108             reg = <0x0ae01000 0x8f000>,
109                   <0x0aeb0000 0x2008>;
125             interrupts = <0>;
129                 #size-cells = <0>;
131                 port@0 {
132                     reg = <0>;
173             reg = <0x0ae94000 0x400>;
194             assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
203             #size-cells = <0>;
207                 #size-cells = <0>;
209                 port@0 {
210                     reg = <0>;
245             reg = <0x0ae94400 0x200>,
246                   <0x0ae94600 0x280>,
247                   <0x0ae94900 0x260>;
253             #phy-cells = <0>;
263             reg = <0x0ae96000 0x400>;
284             assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
293             #size-cells = <0>;
297                 #size-cells = <0>;
299                 port@0 {
300                     reg = <0>;
316             reg = <0x0ae96400 0x200>,
317                   <0x0ae96600 0x280>,
318                   <0x0ae96900 0x260>;
324             #phy-cells = <0>;