display/msm/qcom%2Csm6375-mdss.yaml

1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sm6375-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SM6375 Display MDSS
10   - Konrad Dybcio <konrad.dybcio@linaro.org>
13   SM6375 MSM Mobile Display Subsystem (MDSS), which encapsulates sub-blocks
16 $ref: /schemas/display/msm/mdss-common.yaml#
20     const: qcom,sm6375-mdss
24       - description: Display AHB clock from gcc
25       - description: Display AHB clock
26       - description: Display core clock
28   clock-names:
30       - const: iface
31       - const: ahb
32       - const: core
40   interconnect-names:
44   "^display-controller@[0-9a-f]+$":
48         const: qcom,sm6375-dpu
50   "^dsi@[0-9a-f]+$":
55           - const: qcom,sm6375-dsi-ctrl
56           - const: qcom,mdss-dsi-ctrl
58   "^phy@[0-9a-f]+$":
62         const: qcom,sm6375-dsi-phy-7nm
67   - |
68     #include <dt-bindings/clock/qcom,rpmcc.h>
69     #include <dt-bindings/clock/qcom,sm6375-gcc.h>
70     #include <dt-bindings/clock/qcom,sm6375-dispcc.h>
71     #include <dt-bindings/interrupt-controller/arm-gic.h>
72     #include <dt-bindings/power/qcom-rpmpd.h>
74     display-subsystem@5e00000 {
75         compatible = "qcom,sm6375-mdss";
77         reg-names = "mdss";
79         power-domains = <&dispcc MDSS_GDSC>;
84         clock-names = "iface", "ahb", "core";
87         interrupt-controller;
88         #interrupt-cells = <1>;
91         #address-cells = <1>;
92         #size-cells = <1>;
95         display-controller@5e01000 {
96             compatible = "qcom,sm6375-dpu";
99             reg-names = "mdp", "vbif";
108             clock-names = "bus",
116             assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
117             assigned-clock-rates = <19200000>;
119             operating-points-v2 = <&mdp_opp_table>;
120             power-domains = <&rpmpd SM6375_VDDCX>;
122             interrupt-parent = <&mdss>;
126                 #address-cells = <1>;
127                 #size-cells = <0>;
132                         remote-endpoint = <&dsi0_in>;
139             compatible = "qcom,sm6375-dsi-ctrl", "qcom,mdss-dsi-ctrl";
141             reg-names = "dsi_ctrl";
143             interrupt-parent = <&mdss>;
152             clock-names = "byte",
159             assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
161             assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
163             operating-points-v2 = <&dsi_opp_table>;
164             power-domains = <&rpmpd SM6375_VDDMX>;
167             phy-names = "dsi";
169             #address-cells = <1>;
170             #size-cells = <0>;
173                 #address-cells = <1>;
174                 #size-cells = <0>;
179                         remote-endpoint = <&dpu_intf1_out>;
192             compatible = "qcom,sm6375-dsi-phy-7nm";
196             reg-names = "dsi_phy",
200             #clock-cells = <1>;
201             #phy-cells = <0>;
205             clock-names = "iface", "ref";