display/msm/qcom%2Csm6350-mdss.yaml

1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sm6350-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SM6350 Display MDSS
10   - Krishna Manikandan <quic_mkrishn@quicinc.com>
13   SM6350 MSM Mobile Display Subsystem (MDSS), which encapsulates sub-blocks
14   like DPU display controller, DSI and DP interfaces etc.
16 $ref: /schemas/display/msm/mdss-common.yaml#
20     const: qcom,sm6350-mdss
24       - description: Display AHB clock from gcc
25       - description: Display AXI clock from gcc
26       - description: Display core clock
28   clock-names:
30       - const: iface
31       - const: bus
32       - const: core
40   interconnect-names:
44   "^display-controller@[0-9a-f]+$":
48         const: qcom,sm6350-dpu
50   "^dsi@[0-9a-f]+$":
55           - const: qcom,sm6350-dsi-ctrl
56           - const: qcom,mdss-dsi-ctrl
58   "^phy@[0-9a-f]+$":
62         const: qcom,dsi-phy-10nm
67   - |
68     #include <dt-bindings/clock/qcom,dispcc-sm6350.h>
69     #include <dt-bindings/clock/qcom,gcc-sm6350.h>
70     #include <dt-bindings/clock/qcom,rpmh.h>
71     #include <dt-bindings/interrupt-controller/arm-gic.h>
72     #include <dt-bindings/power/qcom-rpmpd.h>
74     display-subsystem@ae00000 {
75         compatible = "qcom,sm6350-mdss";
77         reg-names = "mdss";
79         power-domains = <&dispcc MDSS_GDSC>;
84         clock-names = "iface", "bus", "core";
87         interrupt-controller;
88         #interrupt-cells = <1>;
91         #address-cells = <1>;
92         #size-cells = <1>;
95         display-controller@ae01000 {
96             compatible = "qcom,sm6350-dpu";
99             reg-names = "mdp", "vbif";
107             clock-names = "bus", "iface", "rot", "lut", "core",
110             assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
114             assigned-clock-rates = <300000000>,
119             interrupt-parent = <&mdss>;
121             operating-points-v2 = <&mdp_opp_table>;
122             power-domains = <&rpmhpd SM6350_CX>;
125                 #address-cells = <1>;
126                 #size-cells = <0>;
131                         remote-endpoint = <&dsi0_in>;
138             compatible = "qcom,sm6350-dsi-ctrl", "qcom,mdss-dsi-ctrl";
140             reg-names = "dsi_ctrl";
142             interrupt-parent = <&mdss>;
151             clock-names = "byte",
158             assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
160             assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
162             operating-points-v2 = <&dsi_opp_table>;
163             power-domains = <&rpmhpd SM6350_MX>;
166             phy-names = "dsi";
168             #address-cells = <1>;
169             #size-cells = <0>;
172                 #address-cells = <1>;
173                 #size-cells = <0>;
178                         remote-endpoint = <&dpu_intf1_out>;
191             compatible = "qcom,dsi-phy-10nm";
195             reg-names = "dsi_phy",
199             #clock-cells = <1>;
200             #phy-cells = <0>;
203             clock-names = "iface", "ref";