display/msm/qcom%2Csm6125-mdss.yaml

1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sm6125-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SM6125 Display MDSS
10   - Marijn Suijten <marijn.suijten@somainline.org>
13   SM6125 MSM Mobile Display Subsystem (MDSS), which encapsulates sub-blocks
16 $ref: /schemas/display/msm/mdss-common.yaml#
20     const: qcom,sm6125-mdss
24       - description: Display AHB clock from gcc
25       - description: Display AHB clock
26       - description: Display core clock
28   clock-names:
30       - const: iface
31       - const: ahb
32       - const: core
40   interconnect-names:
44   "^display-controller@[0-9a-f]+$":
48         const: qcom,sm6125-dpu
50   "^dsi@[0-9a-f]+$":
55           - const: qcom,sm6125-dsi-ctrl
56           - const: qcom,mdss-dsi-ctrl
58   "^phy@[0-9a-f]+$":
62         const: qcom,sm6125-dsi-phy-14nm
67   - |
68     #include <dt-bindings/clock/qcom,dispcc-sm6125.h>
69     #include <dt-bindings/clock/qcom,gcc-sm6125.h>
70     #include <dt-bindings/clock/qcom,rpmcc.h>
71     #include <dt-bindings/interrupt-controller/arm-gic.h>
72     #include <dt-bindings/power/qcom-rpmpd.h>
74     display-subsystem@5e00000 {
75         compatible = "qcom,sm6125-mdss";
77         reg-names = "mdss";
80         interrupt-controller;
81         #interrupt-cells = <1>;
86         clock-names = "iface",
90         power-domains = <&dispcc MDSS_GDSC>;
94         #address-cells = <1>;
95         #size-cells = <1>;
98         display-controller@5e01000 {
99             compatible = "qcom,sm6125-dpu";
102             reg-names = "mdp", "vbif";
104             interrupt-parent = <&mdss>;
114             clock-names = "bus",
121             assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
122             assigned-clock-rates = <19200000>;
124             operating-points-v2 = <&mdp_opp_table>;
125             power-domains = <&rpmpd SM6125_VDDCX>;
128                 #address-cells = <1>;
129                 #size-cells = <0>;
134                         remote-endpoint = <&mdss_dsi0_in>;
141             compatible = "qcom,sm6125-dsi-ctrl", "qcom,mdss-dsi-ctrl";
143             reg-names = "dsi_ctrl";
145             interrupt-parent = <&mdss>;
154             clock-names = "byte",
160             assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
162             assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
164             operating-points-v2 = <&dsi_opp_table>;
165             power-domains = <&rpmpd SM6125_VDDCX>;
168             phy-names = "dsi";
170             #address-cells = <1>;
171             #size-cells = <0>;
174                 #address-cells = <1>;
175                 #size-cells = <0>;
180                         remote-endpoint = <&dpu_intf1_out>;
193             compatible = "qcom,sm6125-dsi-phy-14nm";
197             reg-names = "dsi_phy",
201             #clock-cells = <1>;
202             #phy-cells = <0>;
206             clock-names = "iface",
209             required-opps = <&rpmpd_opp_nom>;
210             power-domains = <&rpmpd SM6125_VDDMX>;